Phase Interpolator Duty Cycle Correction in Low-Power Class B Clocks

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Solution Overview

Problem

Existing digital communication systems face challenges in generating low-power output clock signals with accurate duty cycles and phase interpolation, leading to inefficiencies in power consumption and signal quality.

Innovation Solution

A phase interpolator circuit using four PI quadrant circuits operating in Class B mode, combined with a current mode logic (CML) to CMOS converter, adjusts phase and duty cycle through a feedback loop, generating output clock signals from four input clocks with sub-picosecond precision and reduced power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If Class B operation mode is used to reduce power consumption, then power efficiency is improved, but duty cycle accuracy deteriorates

Engineering Contradiction:

Improvepower consumptionVSAvoidduty cycle accuracy

Core Design Contradiction:

Use of energy by moving objectVSManufacturing precision

Solution Approach 1:

The patent implements a feedback mechanism where the duty cycle of the output clock signal is monitored and fed back to adjust the common mode voltage of the PI quadrant circuits. This closed-loop control compensates for duty cycle errors introduced by Class B operation, maintaining accuracy while preserving power efficiency benefits.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The patent dynamically adjusts the common mode voltage parameter of the PI quadrant circuits based on the measured duty cycle error. By changing this voltage parameter in response to feedback, the system corrects duty cycle inaccuracies without transitioning out of Class B operation mode, thus maintaining low power consumption.

Inventive Principle:

Principle #35Parameter changes

2Measurement precision

If phase interpolation precision is improved to sub-picosecond levels, then signal quality is improved, but circuit complexity increases

Engineering Contradiction:

Improvephase interpolation precisionVSAvoidcircuit complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The patent divides the phase interpolation function into four separate PI quadrant circuits, each handling a specific 90-degree phase range. This segmentation allows each quadrant to operate independently with optimized biasing, achieving sub-picosecond precision while keeping individual circuit blocks manageable in complexity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent employs dynamic bias control where the common mode voltage of each PI quadrant is adjusted in real-time based on feedback from the output duty cycle measurement. This dynamic adjustment mechanism enables high precision phase interpolation without requiring overly complex static circuit design.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS12375073B1Low power phase interpolator with duty cycle correction

Publication Date: 2025.07.29 CISCO TECHNOLOGY INC

AI summary

In part, the disclosure relates to a source generating four input clock signals; a phase interpolator (PI) circuit that includes four PI quadrant circuits and a PI bias control circuit, wherein each PI quadrant circuit is configured to: receive, via the source, an input clock signal of the four input clock signals, and generate, based on the input clock signal, a pair of intermediate output clock signals of complementary phases; and a current mode logic (CML) to complementary metal-oxide-semiconductor (CMOS) converter.