Phase Interpolator Duty Cycle Correction for Low-Latency CDR

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Solution Overview

Problem

Developing a circuit architecture for high-speed serial links that effectively performs clock data recovery (CDR) and duty cycle correction (DCC) while meeting strict requirements for linearity, granularity, power consumption, and latency, and avoiding cross contention between tristate inverter pairs.

Innovation Solution

Integration of phase interpolation (PI) and duty cycle correction (DCC) functions within a single circuit, decoupling control codes for p-type and n-type networks, and blending DCC mechanisms into the PI mixer code decoding scheme to enable low latency and efficient phase interpolation and duty cycle correction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by stationary object

If separate PI and DCC circuits are used, then functionality is complete, but power consumption increases and device complexity increases

Engineering Contradiction:

Improvepower consumptionVSAvoidcircuit architecture

Core Design Contradiction:

Use of energy by stationary objectVSDevice complexity

Solution Approach 1:

The patent combines the phase interpolation (PI) mixer and duty cycle correction (DCC) circuits into a single integrated unit. The DCC circuit is merged with the PI mixer such that the tristate inverter pairs serve dual purposes: phase interpolation and duty cycle correction, eliminating the need for separate DCC circuitry while maintaining both functions

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The tristate inverter pairs in the integrated circuit perform multiple functions simultaneously. They act as both phase interpolators and duty cycle correctors, making the circuit elements universal and multi-functional, which reduces overall device complexity and power consumption

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Device complexity

If separate PI and DCC circuits are used, then functionality is complete, but device complexity increases

Engineering Contradiction:

Improvecircuit architectureVSAvoidpower consumption

Core Design Contradiction:

Device complexityVSUse of energy by stationary object

Solution Approach 1:

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Loss of time

If traditional DCC circuits are used, then duty cycle correction is achieved, but latency increases

Engineering Contradiction:

ImproveCDR loop latencyVSAvoidduty cycle correction accuracy

Core Design Contradiction:

Loss of timeVSReliability

Solution Approach 1:

The duty cycle correction is performed concurrently with phase interpolation in the same clock cycle, rather than sequentially. The DCC circuit is designed to correct duty cycle while the PI mixer is interpolating phases, eliminating additional latency stages and achieving low-latency operation

Inventive Principle:

Principle #10Preliminary action

4Reliability

If slow duty cycle adjustment circuits are used, then duty cycle correction is achieved, but aging risk increases due to short circuit current

Engineering Contradiction:

Improveaging riskVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The patent converts the potential harmful short circuit current issue into a beneficial feature by using the same tristate inverter pairs for both phase interpolation and duty cycle correction. The controlled switching nature of tristate inverters naturally prevents short circuit conditions while maintaining low power consumption, eliminating aging risks associated with traditional DCC circuits

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS11088682B2High speed digital phase interpolator with duty cycle correction circuitry

Publication Date: 2021.08.10 INTEL CORP

AI summary

Described is a circuit and architecture that combines phase interpolator (PI) mixer with duty cycle correction (DCC), to prevent cross contention between the tristate inverter pairs of the mixer. The control code for the p-type and n-type networks in the PI mixer are decoupled, and DCC mechanism are blended in the PI mixer code decoding scheme to enable a low latency phase interpolation and duty cycle correction. The circuit comprises a first mixer circuitry controllable by a first code; a second mixer circuitry controllable by a second code; a node coupled to outputs of the first and second mixers; and a keeper circuitry coupled to the node, wherein the first and second mixers are tri-stable mixers.