Phase Interpolator Feedback Correction for Stable Clock Phase Difference
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Solution Overview
Problem
Conventional phase interpolator circuits in Serializer/Deserializer (SerDes) systems experience phase difference shifts between output clock signals due to skew mismatch, leading to reduced timing margins and hindered high-speed operations.
Innovation Solution
A phase interpolator circuit with a correction circuit that adjusts the current amount of intermediate currents based on a correction code to maintain a constant phase difference between output clock signals, using transistors and resistors to synthesize and correct phase errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional phase interpolator circuits are used to generate output clock signals, then the circuit can operate at high speed, but phase difference shifts occur between output clock signals due to skew mismatch, reducing timing margins
Solution Approach 1:
The patent implements a feedback mechanism where the phase difference between first and second output clock signals is detected and used to control a current amount adjustment circuit. This circuit adjusts the current supplied to the second phase interpolator based on the detected phase difference, creating a closed-loop system that automatically corrects phase skew and maintains stable timing relationships while preserving high-speed operation.
2Adaptability or versatility
If phase interpolation is performed using multiple input clock signals, then the desired phase can be generated, but skew mismatch between input clocks causes phase difference shifts in output clocks
Solution Approach 1:
The patent changes the current parameter supplied to the second phase interpolator based on the detected phase difference. By dynamically adjusting the current amount control signal, the system compensates for skew mismatch effects and maintains accurate phase difference relationships between output clock signals, enabling precise phase generation despite input clock variations.
3Ease of operation
If the phase interpolator circuit generates output clock signals with adjusted phase, then data acquisition from reception signal is enabled, but timing margins are reduced due to phase difference shifts
Solution Approach 1:
The feedback mechanism detects phase differences between output clock signals and uses this information to adjust the current supplied to the second phase interpolator. This closed-loop control eliminates phase difference shifts that would otherwise reduce timing margins, thereby preserving adequate time margins for reliable data acquisition from the reception signal.
Data Source
AI summary
A phase interpolator circuit that generates an output clock signal having a phase according to a PI code based on input clock signals, the phase interpolator circuit includes: a first generation circuit configured to generate a first intermediate current based on a first input clock signal according to the PI code; a second generation circuit configured to generate a second intermediate current based on a second input clock signal having a first phase difference from the first input clock signal according to the PI code; a synthesis circuit configured to synthesize the first and second intermediate currents to generate the output clock signal; and a correction circuit configured to correct a current amount of at least one of the intermediate currents based on a correction current according to a correction code set according to at least an amount of shift of the first phase difference from a certain value.