Phase Interpolator Clock Switching to Prevent Glitches
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional phase interpolators experience glitches during clock signal switching due to transient effects, leading to operational abnormalities.
Innovation Solution
A clock signal selector with a selection signal generator that sets a set time point based on the transition point of one clock signal whose phase lags behind the other, generating a selection signal to prevent incomplete transitions and glitches during switching operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the clock signal switching operation is executed at the transition point of the clock signal, then the switching speed is improved, but a glitch is generated due to transient effects
Solution Approach 1:
The selection signal generator executes the clock signal switching operation in advance at a predetermined time point before the transition point of the clock signal. This preliminary action ensures that the selector has sufficient time to complete the switching operation before the clock signal transitions, avoiding the transient effects that cause glitches while maintaining reliable signal output.
2Reliability
If the clock signal switching operation is executed early to avoid glitches, then signal stability is improved, but switching delay increases
Solution Approach 1:
The system performs the switching operation preliminarily at a predetermined time point that is calculated based on the known transition characteristics of the clock signal. This approach optimizes the timing to achieve the minimum necessary advance execution, thereby reducing switching delay while still preventing glitches caused by transient effects.
3Measurement precision
If the selector switches clock signals at the transition point, then the phase interpolation precision is improved, but operational abnormalities occur due to glitches
Solution Approach 1:
By executing the switching operation at a predetermined time point before the clock signal transition point, the selector completes the switching action before the transition occurs. This timing arrangement maintains precise phase interpolation because the switching is synchronized to the known transition characteristics, while simultaneously preventing glitches that would cause operational abnormalities.
Data Source
AI summary
A phase interpolator capable of preventing a glitch from being generated during a clock signal switching operation and a clock signal selector thereof are provided. The clock signal selector includes a selector and a selection signal generator. The selector receives multiple clock signals with different phases. The selector selects one of the clock signals according to a selection signal to generate a selected clock signal. The selection signal generator is coupled to the selector and generates the selection signal. When the selector switches from selecting a first clock signal to selecting a second clock signal as the selected clock signal, the selection signal generator generates a set time point according to a transition point of one of the first clock signal and the second clock signal whose phase lags behind a phase of the other, and generates the selection signal according to the set time point.