Hybrid Phase Interpolator Coding for Low-Jitter Clock Recovery
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Solution Overview
Problem
Phase interpolators in clock data recovery circuits suffer from excessive clock jitter due to nonlinearity, which degrades the recovered clock signal quality.
Innovation Solution
Combining current coding and size coding schemes in phase interpolators by using a pair of load resistors, differential pairs of transistors, and switches to control current and phase interpolation, thereby improving linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a phase interpolator is used in a clock data recovery circuit, then the circuit can generate precisely-aligned clocks by interpolating between reference phases, but the nonlinearity of the phase interpolator introduces excessive clock jitter that degrades the recovered clock signal quality
Solution Approach 1:
The patent combines two different coding schemes (current coding and size coding) into a single hybrid phase interpolator architecture. The current coding portion handles coarse phase interpolation while the size coding portion handles fine phase interpolation, merging their advantages to achieve both high precision and low jitter performance
Solution Approach 2:
The patent applies different coding schemes to different portions of the phase interpolator based on their specific functions. The current coding portion uses equal-sized current sources for coarse interpolation, while the size coding portion uses variable-sized current sources for fine interpolation, optimizing each portion's characteristics for its specific purpose
2Productivity
If a dual-loop CDR architecture with phase interpolator is used, then the system can recover data from serialized signals, but the nonlinearity introduces differential nonlinearity (DNL) that severely degrades the recovered clock jitter
Solution Approach 1:
The patent merges current coding and size coding schemes to achieve superior linearity characteristics. The combination ensures that both coarse and fine phase steps maintain consistent amplitude relationships, minimizing differential nonlinearity across the entire phase range
Solution Approach 2:
The patent changes the coding scheme parameters by using different current source configurations in different portions of the interpolator. The size coding portion uses current sources with amplitudes in fixed ratios (e.g., 1:2:4:8) while the current coding portion uses equal-sized sources, optimizing the phase step linearity
Data Source
AI summary
A phase interpolator, including: a first portion including a first plurality of branches and a plurality of tail current sources, each branch including a differential pair of transistors, source terminals of the differential pair of transistors connect to form a source node, wherein each tail current source couples to one of the source nodes, and wherein the differential pair of transistors and the corresponding tail current source are configured in a current coding scheme; a second portion including a second plurality of branches and a fixed current source coupled to the second plurality of branches, each branch of the second plurality of branches including a second plurality of differential pairs of transistors and a plurality of switches configured in a size coding scheme; wherein the first portion and the second portion are coupled to each other and to a pair of load resistors.