Balanced Phase Interpolator Layout for Lower INL and DNL
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Solution Overview
Problem
Existing phase interpolators in high-speed communication systems suffer from sub-optimal integral non-linearity (INL) and differential non-linearity (DNL) characteristics, leading to inconsistent output and inaccuracies, despite having improved power consumption and area characteristics.
Innovation Solution
A phase interpolator design with a balanced layout and a bleeder path that includes an arrayed or mirrored layout of functional units and a bleeder path to improve INL and DNL performance, ensuring more accurate phase interpolation and data recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a phase interpolator is designed with improved power consumption and area characteristics, then power efficiency and compactness are enhanced, but integral non-linearity (INL) and differential non-linearity (DNL) characteristics deteriorate
Solution Approach 1:
The phase interpolator is divided into multiple functional units (e.g., multiple delay cells or phase shifting stages) that can be independently controlled. Each functional unit processes a portion of the phase adjustment, allowing for finer granularity in phase control and improved linearity characteristics while maintaining compact area and reasonable power consumption through modular architecture.
Solution Approach 2:
Different functional units within the phase interpolator are designed with locally optimized characteristics. Specifically, units operating in different phase ranges or handling different signal paths may have tailored delay characteristics or buffering structures, ensuring that each local region contributes optimally to overall INL and DNL performance while adapting to the compact design constraints.
2Area of stationary object
If a phase interpolator is designed with improved power consumption and area characteristics, then device compactness is enhanced, but output consistency and accuracy deteriorate
Solution Approach 1:
Multiple phase adjustment functions are merged into a unified functional unit structure. By combining delay elements, buffering stages, and control logic into integrated functional blocks, the design achieves compact area utilization while maintaining consistent output characteristics through coordinated operation of the merged components.
Solution Approach 2:
The functional units are designed to operate at matched potential levels, ensuring that signal integrity and timing characteristics remain consistent across different phase output levels. This equipotential design approach maintains output accuracy and consistency throughout the compact structure by balancing electrical characteristics across all functional units.
3Manufacturing precision
If functional units are arranged in an arrayed or mirrored layout, then INL and DNL performance are improved, but layout complexity increases
Solution Approach 1:
While the overall architecture employs symmetric arrayed or mirrored layouts for matching characteristics, the internal arrangement of individual functional units utilizes asymmetric optimization. This allows the external symmetric structure to provide good INL and DNL performance while the internal asymmetric details reduce inter-unit variability and simplify manufacturing, effectively managing layout complexity.
Solution Approach 2:
The design uses replicated functional unit templates that can be copied and arranged in arrayed or mirrored configurations. By creating a standardized functional unit cell that can be repeatedly instantiated, the complex layout is simplified through modular copying, ensuring consistent INL and DNL performance across all units while reducing the complexity of individual unit design.
Data Source
AI summary
Circuits, devices, and methods relating to a phase interpolator are described herein. The phase interpolator may comprise a first plurality of functional units and a second plurality of functional units, and may be controlled, in part, by an encoding scheme. The phase interpolator may be designed to have a layout such that a turn-on resistance across the first plurality of functional units in response to a first code of the encoding scheme is equal to a turn-on resistance across the second plurality of functional units in response to a second code of the encoding scheme.