Phase Interpolator Calibration for Deterministic Jitter Reduction
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Solution Overview
Problem
Data communication systems, particularly those using passive optical networks (PON), face challenges in managing deterministic jitter caused by non-ideal phase interpolators, which affect the accuracy of clock signals and data transmission.
Innovation Solution
A system comprising multiple phase interpolators and calibration circuits that adjust phase control signals to minimize jitter by maintaining an integer ratio of frequencies between transmit and receive clocks, using a control and calibration circuit to measure phase offsets and tune the phase relationship between transmitter and receiver phase interpolators to achieve local minima in interference patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If phase interpolators are used to adjust transmit and receive phases, then frequency matching between transmitter and receiver is improved, but deterministic jitter increases due to non-ideal phase interpolator behavior
Solution Approach 1:
The patent applies preliminary action by performing calibration of the phase interpolators before normal operation. The calibration process pre-determines the relationship between phase control codes and actual phase shifts, storing this calibration data for use during operation. This preliminary calibration step eliminates deterministic jitter by establishing accurate phase relationships in advance, rather than attempting to correct jitter during data transmission.
Solution Approach 2:
The patent changes the parameter of phase control codes during calibration to map the actual phase shifts of the phase interpolators. By varying the phase control codes and measuring the corresponding phase differences, the system creates a calibration lookup table that accounts for non-ideal behavior. This parameter transformation allows the system to compensate for deterministic jitter by selecting corrected phase codes during operation.
2Measurement precision
If phase control codes are adjusted to compensate for phase differences, then phase alignment between transmit and receive clocks is improved, but jitter margins are reduced due to interference patterns
Solution Approach 1:
The patent implements feedback by measuring the actual phase difference between transmit and receive clocks and using this measurement to adjust phase control codes. The calibration process continuously monitors phase alignment and feeds this information back to determine the optimal phase offset. This feedback mechanism ensures that phase alignment is maintained while avoiding interference patterns that would reduce jitter margins, as the system adapts to the actual hardware behavior rather than relying on theoretical models.
3Reliability
If deterministic jitter is reduced through calibration, then data transmission reliability is improved, but system complexity increases due to additional calibration circuits
Solution Approach 1:
The patent merges the calibration functionality with the existing phase interpolator structure by integrating calibration circuits into the SERDES block. The calibration process uses the same phase interpolators and clock recovery circuits that are already present in the system, rather than adding completely separate calibration hardware. This merging approach reduces the overall complexity increase while still achieving deterministic jitter reduction through the calibration process.
Data Source
AI summary
A system for controlling jitter includes a first phase interpolator, a second phase interpolator, a first circuit configured to receive a first signal provided to the first phase interpolator, a second circuit configured to receive a second signal provided to the second phase interpolator, and a third circuit configured to provide a phase control signal in response to the first signal and the second signal. The first signal represents a first phase adjustment, and the second signal represents a second phase adjustment.