Phase Interpolator Clock Recovery to Reduce Jitter and Glitches
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Solution Overview
Problem
Phase interpolators in integrated circuit devices experience significant output period jitter due to abrupt changes in clock signal phases, particularly in CMOS PI devices, which can lead to glitches and malfunction in data transmission.
Innovation Solution
The implementation of a circuit and method that generates multiple phase interpolator control signals during a clock cycle based on a phase interpolator code, reducing the step size of changes in the CDR code at both the rising and falling edges of the clock signal, and selecting codes based on detected boundary crossings to minimize glitches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a clock phase interpolator generates an arbitrary clock phase based on an input digital code, then the clock phase can be adjusted to track data edges, but the output clock experiences extended period jitter when the code changes by many steps
Solution Approach 1:
The patent segments the single large code change into multiple smaller code changes distributed across different clock cycles. The phase interpolator code is updated in steps rather than all at once, breaking down the abrupt phase transition into manageable increments that reduce jitter while still achieving the desired phase tracking.
Solution Approach 2:
The patent performs preliminary action by preparing and applying phase interpolator code changes in advance across multiple clock cycles before the full phase adjustment is needed. The CDR code is modified gradually in predetermined steps, allowing the system to prepare for the phase transition smoothly rather than making abrupt changes.
2Speed
If the phase interpolator code changes abruptly to track data edges, then the clock can respond quickly to data movements, but significant period jitter and glitches occur in the output
Solution Approach 1:
The patent segments the abrupt code change into a sequence of smaller code changes applied over multiple clock cycles. This segmentation maintains the ability to respond to data edge movements while eliminating the harmful jitter and glitches that result from sudden large code transitions.
Solution Approach 2:
The patent implements periodic action by distributing code changes across multiple clock cycles in a structured sequence. Rather than making a single abrupt change, the phase interpolator code is updated periodically in small steps, transforming the harmful abrupt transition into a controlled periodic adjustment that eliminates jitter.
3Reliability
If multiple phase interpolator control signals are generated during a clock cycle, then the CDR code changes can be distributed to reduce step size, but the circuit complexity increases
Solution Approach 1:
The patent uses preliminary action by pre-determining the sequence of code changes to be applied. The CDR circuit prepares the phase interpolator code updates in advance according to a predetermined multi-step sequence, allowing multiple control signals to be generated systematically without requiring complex real-time decision logic.
Solution Approach 2:
The patent implements feedback mechanisms where the CDR circuit monitors the phase interpolator code and adjusts subsequent code changes based on the current state. This feedback approach allows the generation of multiple control signals in a coordinated manner, reducing jitter while managing circuit complexity through intelligent control rather than brute-force complexity.
Data Source
AI summary
A circuit for receiving a signal in an integrated circuit is described. The circuit comprises a sampler configured to receive an input data signal, wherein the sampler generates sampled data and a recovered clock; a clock and data recovery circuit configured to receive the sampled data and the recovered clock and to generate a phase interpolator code; and a phase interpolator configured to receive the phase interpolator code; wherein the phase interpolator generates multiple phase interpolator control signals during a clock cycle based upon the phase interpolator code generated for the clock cycle.