Phase Interpolator Clock Recovery With Reduced Period Jitter
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Solution Overview
Problem
Phase interpolators in CMOS integrated circuit devices experience significant output period jitter due to abrupt changes in clock phase codes, particularly in glitch-sensitive applications, leading to potential malfunctions in downstream circuits.
Innovation Solution
The proposed solution involves generating multiple phase interpolator control signals during a clock cycle, reducing the step size of changes in clock and data recovery codes, and adjusting the phase of a multi-phase clock to minimize glitches by implementing a clock and data recovery loop that captures and adjusts phase interpolator codes during both halves of a clock cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a clock phase interpolator generates an arbitrary clock phase based on an input digital code, then the output clock phase can track data edges, but the output clock experiences extended big period jitter when the code changes by many steps at a time
Solution Approach 1:
The patent divides a large phase code change into multiple smaller incremental steps. Instead of applying the full code change immediately, the phase interpolator breaks it down into smaller segments that are applied sequentially over multiple clock cycles, preventing large abrupt phase transitions that cause jitter.
Solution Approach 2:
The patent implements a preliminary action by pre-calculating and buffering phase code changes before they are applied to the phase interpolator. The system prepares the phase adjustment in advance and applies it gradually, ensuring smooth transitions without sudden jumps that would cause period jitter.
2Speed
If a phase interpolator uses abrupt changes in clock phase codes to quickly adjust to data edges, then the tracking speed improves, but output period jitter increases causing potential malfunctions in downstream circuits
Solution Approach 1:
The patent implements dynamic phase adjustment where the size of phase code steps is adapted based on the current tracking error and system state. When the phase error is large, larger steps are used to quickly reduce the error, but as the phase approaches the target, the step size decreases to prevent overshoot and jitter, creating a dynamic balancing act between speed and stability.
Data Source
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AI summary
A circuit for receiving a signal in an integrated circuit is described. The circuit comprises a sampler (202) configured to receive an input data signal, wherein the sampler generates sampled data and a recovered clock; a clock and data recovery circuit (204) configured to receive the sampled data and the recovered clock and to generate a phase interpolator code; and a phase interpolator (206) configured to receive the phase interpolator code; wherein the phase interpolator generates multiple phase interpolator control signals during a clock cycle based upon the phase interpolator code generated for the clock cycle.