Phase Interpolator Circuit for Linear Phase Control
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Solution Overview
Problem
Existing phase interpolation methods suffer from non-linear phase output versus transconductance bias current correlation, especially for large phase differences, and parasitic capacitance between transistors leads to phase falsification, particularly for extreme weightings.
Innovation Solution
The method involves superimposing two additional input signals with phases shifted by half of the phase difference between the primary input signals, allowing for parallel phase interpolators to compensate non-linearities and achieve higher linearity by adjusting weighting ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a larger number of input signals are provided to improve linearity, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The phase interpolation process is segmented into multiple stages: first generating 12 equidistant input signals, then selecting adjacent pairs for fine interpolation. This segmentation allows achieving high linearity through multiple small interpolation steps rather than one large interpolation, thereby improving manufacturing precision without proportionally increasing device complexity.
Solution Approach 2:
The patent transitions from direct phase interpolation to a two-dimensional approach: first interpolating in the frequency domain by generating multiple equidistant input signals, then performing fine interpolation in the phase domain. This dimensional transformation enables higher linearity while controlling circuit complexity through systematic signal generation.
2Adaptability or versatility
If transconductance stages are arranged in parallel to enable weighted superposition, then adaptability is improved, but object-generated harmful factors worsen due to parasitic capacitance
Solution Approach 1:
The patent converts the harmful effect of parasitic capacitance into a beneficial one by deliberately introducing compensation capacitances that match the parasitic values. These compensation elements, when connected in parallel with the transconductance stages, cancel out the phase falsification caused by parasitic capacitance, thereby maintaining adaptability while eliminating the harmful effect.
Solution Approach 2:
Compensation capacitances are introduced as intermediary elements between the transconductance stages and the output node. These intermediary capacitances act as mediators that counterbalance the parasitic capacitance effects, allowing the parallel transconductance arrangement to maintain its adaptability for weighted superposition while eliminating phase falsification.
Data Source
AI summary
The invention relates to the generation of an electric output signal with a specified frequency and a phase (P) dependent upon a control signal (x) by means of weighted superposition of several input signals (s1, s2, s1*, s2*), which have the specified frequency but different input signals phases, whereby the weighted superposition is applied to a parallel switching of adjustable transconductance stages which are each adjusted by the control signal (x) and to each of which one of the input signals (s1, s2, s1*, s2*) is supplied. In order to be able to use this so-called phase interpolation to meet higher linearity requirements, the invention provides that for the generation of the output signal with a phase which lies between a first input signal phase (0°) of a first input signal (s1) and a second input signal phase (120°) of a second input signal (s2) which second phase is larger by a phase difference (120°), the first input signal (s1) and the second input signal (s2) and two further input signals (s1*1, s2*1 and S1*2, s2*2 resp.) are superimposed in a weighted fashion, whereby the two further input signals (s1*1, s2*1 and S1*2, s2*2 resp.) have phases different by the phase difference (120°) and are phase-shifted by one half (60°) of the phase difference with regard to the first and second input signals (s1, s2).