Resistor-Based Phase Interpolator for Linear Clock Swing
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Solution Overview
Problem
Conventional phase interpolators suffer from asymmetry in charging and discharging rates due to differential pair circuits and current source circuits, leading to inaccurate output common mode levels and poor linearity, especially under process variations and high output clock signal swings.
Innovation Solution
The phase interpolator employs a plurality of phase buffer circuits with first and second resistors and switches to generate an output clock signal, setting a common mode level using resistors and maintaining linearity by dividing supply and ground voltages, thereby stabilizing the output node's common mode level despite process variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If differential pair circuits and current source circuits are used to control current, then the phase interpolator can generate output clock signals, but the charging and discharging rates become asymmetric leading to poor linearity
Solution Approach 1:
The patent extracts and removes the differential pair circuit and current source circuit from the phase interpolator. Instead, it uses a current mirror circuit with PMOS transistors and resistors to control current, eliminating the asymmetric charging/discharging problem inherent in differential pair configurations while maintaining phase interpolation functionality
Solution Approach 2:
The patent changes the circuit topology from differential pair to current mirror configuration, and adjusts the transistor width-to-length ratios (WP1-WP4 and LP1-LP2) to ensure symmetric charging and discharging rates. This parameter optimization ensures that the PMOS transistors operate in saturation region with matched characteristics, improving linearity
2Ease of manufacture
If inverter-based circuits are used, then the phase interpolator can be implemented, but process variations cause offset differences between P-type and N-type transistors leading to inaccurate output common mode level
Solution Approach 1:
The patent uses homogeneous PMOS transistors (P1-P4) with matched width-to-length ratios in a current mirror configuration. All transistors are of the same type (PMOS) with identical dimensions, ensuring symmetric operation and eliminating the offset mismatches that occur when mixing P-type and N-type transistors as in inverter-based designs
Solution Approach 2:
The current mirror circuit with matched PMOS transistors and resistors creates equipotential conditions at the output, ensuring that the common mode level remains accurate and stable despite process variations. The symmetric current paths through P1-P2 and P3-P4 ensure equal voltage drops and potential levels
3Strength
If the swing of the output clock signal is too high, then the signal amplitude is sufficient, but transistors operate in nonlinear region resulting in poor linearity
Solution Approach 1:
The patent dynamically controls the operation region of PMOS transistors through the current mirror configuration. By adjusting the reference current and transistor dimensions, the circuit maintains transistors in the saturation region across the full output swing range, ensuring linear operation even at high amplitude signals. The dynamic biasing through resistors RP1-RP2 and matched transistors keeps the operating point stable
Data Source
AI summary
A phase interpolator includes phase interpolator circuitries. The phase interpolator circuitries generate an output clock signal from an output node according to phase control bits and clock signals. Phases of the clock signals are different from each other. Each phase circuitry includes phase buffer circuits. Each phase buffer circuit is turned on according a first bit and a second bit of the phase control bits, in order to generate a signal component in the output clock signal according to a corresponding clock signal of the clock signals. Each phase buffer circuit includes a first resistor and a second resistor, and transmits one of a first voltage and a second voltage to the output node according to the corresponding clock signal, in which the first voltage is transmitted to the output node via the first resistor, and the second voltage is transmitted to the output node via the second resistor.