Phase Interpolator Linearity Test via Time-Domain Jitter Analysis
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional linearity tests for phase interpolators in chips are costly due to the need for internal phase signal pins and oscilloscope measurements.
Innovation Solution
A linearity test method and system that provide a reference clock signal and a receiver input signal with a phase difference in time domain to the chip under test, allowing for linearity analysis through jitter tolerance testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If internal phase signal pins are applied to the chip for conventional linearity testing, then measurement accuracy is improved, but testing cost increases
Solution Approach 1:
The patent extracts only the essential testing function by removing the need for internal phase signal pins and oscilloscope connections. The linearity test is performed by providing only two external signals (reference clock signal and receiver input signal) to the chip, eliminating complex external measurement equipment while maintaining measurement capability through the chip's existing phase interpolator functionality
Solution Approach 2:
The chip's phase interpolator is made to serve its own testing function by processing the provided reference clock and receiver input signals internally. The chip generates multiple phase signals through its phase interpolator circuitry, and the system determines linearity by analyzing the relationship between input signals and generated phase signals, allowing the chip to test itself without external measurement equipment
2Measurement precision
If multiple internal phase signal pins are used for testing, then linearity analysis capability is improved, but testing time increases
Solution Approach 1:
The patent uses periodic clock signals (reference clock signal) as input to the phase interpolator. By providing periodic signals with known characteristics and analyzing the phase relationships of the generated signals, the system can determine linearity through temporal patterns rather than requiring multiple simultaneous measurement points, thereby reducing testing time while maintaining analysis capability
Data Source
AI summary
A linearity test system for a chip, a linearity signal providing device, and a linearity test method for the chip are provided. The linearity test method for the chip includes steps as follows: providing a reference clock signal and a receiver input signal to a chip under test, wherein the reference clock signal and the receiver input signal have a phase difference in time domain; and determining a linearity of a phase interpolator of the chip under test based on a plurality of phase signals of the chip under test corresponding to the reference clock signal and the receiver input signal.