Phase Interpolator Load Switching for Glitch-Free Mode Transitions
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Solution Overview
Problem
Phase interpolator circuits face issues with glitching during mode transitions between direct current (DC) and alternating current (AC) modes, leading to unpredictability in downstream logic due to incompatibility of feedback control loops and resulting duty cycle distortion and integral nonlinearity errors.
Innovation Solution
Incorporating both static and dynamic loads in phase interpolator circuits, allowing initial operation with static loads to prevent glitching, followed by gradual transition to dynamic loads once output signals stabilize, thereby reducing duty cycle distortion and integral nonlinearity errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a feedback control loop is used to reduce duty cycle distortion and integral nonlinearity errors, then measurement precision is improved, but the system becomes incompatible with static operation in DC mode because the loop forms a high pass function that leaves the output undetermined
Solution Approach 1:
The patent applies dynamics by making the load type changeable based on operating mode. The system dynamically switches between static loads for DC mode and dynamic loads for AC mode, allowing the phase interpolator to adapt its characteristics to the required operating condition. This resolves the contradiction by enabling the system to have different load configurations for different modes rather than being fixed to one type.
Solution Approach 2:
The patent changes the fundamental parameter of load type (static vs. dynamic) based on the operating mode requirement. For DC mode, static loads are used to provide stable bias points, while for AC mode, dynamic loads are engaged to enable feedback control. This parameter change allows the system to optimize performance for each mode without being constrained by a single load configuration.
2Measurement precision
If dynamic loads are used to output AC signals and reduce duty cycle distortion, then measurement precision is improved, but glitching occurs during mode transitions that creates unpredictability in downstream logic
Solution Approach 1:
The patent applies preliminary action by preparing the static load configuration before switching to dynamic load mode. The static loads are maintained during transitions to provide continuous stable bias points, preventing glitching before it can occur. This advance preparation ensures that downstream logic remains predictable throughout the mode transition process.
Solution Approach 2:
The patent uses static loads as an intermediary during mode transitions between DC and AC modes. The static loads act as a buffer that maintains stable output during the switching process, mediating between the two operating modes and preventing direct conflict that would cause glitching. This intermediary element ensures smooth transitions without disrupting downstream logic.
3Reliability
If static loads are used to prevent glitching during mode transitions, then reliability is improved, but duty cycle distortion and integral nonlinearity errors increase
Solution Approach 1:
The patent makes the load configuration dynamic rather than static, allowing the system to switch between static loads (for reliability during transitions) and dynamic loads (for precision during steady-state AC operation). This dynamic adaptation resolves the contradiction by enabling the system to have different load types at different times based on operational requirements.
Solution Approach 2:
The patent implements periodic switching between static and dynamic load configurations based on the operating mode requirements. Static loads are engaged during DC mode and transition periods, while dynamic loads are engaged during AC mode for optimized performance. This periodic alternation allows the system to capture the benefits of both load types without suffering from their respective drawbacks continuously.
Data Source
AI summary
A system includes a mixer of a phase interpolator. The mixer includes a dynamic load whose output signal is coupled to a subsequent stage of the phase interpolator. The dynamic load is configured to provide an alternating current (AC) signal to the subsequent stage of the phase interpolator as input clock signals. The mixer further includes a static load whose output signal is coupled to the subsequent stage of the phase interpolator in parallel with the respective output signal line of the dynamic load. The static load configured to provide a direct current (DC) signal to the phase interpolator temporarily in replacement of the respective AC signals to prevent output signals of the subsequent stage of the phase interpolator from being unpredictable.