Derivative-Corrected Phase Interpolator for PVT-Stable Timing
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Solution Overview
Problem
Phase interpolators in digital and mixed digital-analog circuits face limitations due to integral non-linearity, which restrict the accuracy of timing control and are challenging to compensate for variations in process, voltage, temperature, and frequency conditions.
Innovation Solution
A phase interpolator system that uses a controller to apply error correction based on the mathematical derivative of phase interpolator error correction data, allowing for a smaller error correction data table and dynamic adjustment of error correction data to compensate for non-linear delay behavior, reducing the required storage space and improving precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional PLLs are used to generate timing clocks, then the circuit structure is simple, but the phase precision and timing control accuracy are insufficient
Solution Approach 1:
The phase interpolator divides the phase adjustment range into multiple segments by using multiple input clocks with different phases (e.g., four input clocks spaced 90 degrees apart). Each input clock controls a portion of the output phase range, allowing precise phase control through digital selection and combination of these segmented phases.
Solution Approach 2:
The phase interpolator acts as an intermediary component between the PLL and the timing control circuitry. It receives a coarse phase control signal from the PLL and interpolates it to generate fine-adjusted phase signals, thereby enhancing the overall phase precision without requiring the PLL itself to be highly complex.
2Measurement precision
If phase interpolators are used to improve timing control precision, then the phase precision is improved, but integral non-linearity limits the accuracy
Solution Approach 1:
The system dynamically adjusts the phase interpolation by selecting different input clock combinations based on the desired output phase. This dynamic selection allows the phase interpolator to adapt to different timing requirements and compensate for non-linearities by choosing optimal input combinations that maintain accuracy across varying conditions.
Solution Approach 2:
The system changes the operational parameters of the phase interpolator by varying the weights or contributions of different input clocks based on process, voltage, and temperature conditions. This allows the interpolator to maintain accurate phase control despite PVT variations by adapting to the changing characteristics of the input clocks.
3Measurement precision
If error correction data is stored in a large table to compensate for non-linear delay behavior, then the timing precision is improved, but the die area increases
Solution Approach 1:
The error correction is applied in segments by dividing the phase range into multiple regions, each with its own correction characteristics. Instead of storing a single large correction table, the system applies smaller correction tables or correction factors to different segments, reducing the total storage requirement while maintaining overall timing precision.
Solution Approach 2:
The system applies partial error correction by focusing on the most significant non-linearities rather than attempting to correct all possible errors. This selective correction approach achieves sufficient timing precision without requiring a complete and exhaustive error correction table, thereby reducing die area.
Data Source
AI summary
Apparatuses and methods for phase interpolators are provided. An example apparatus comprises a phase interpolator and a controller coupled to the phase interpolator. The controller is configured to provide a digital timing code to the phase interpolator, and the phase interpolator is configured to apply a correction to the received digital timing code based, at least in part, on phase interpolator error correction data from a data structure containing phase interpolator error correction data.