Phase Interpolator Input Timing for Glitch-Free Clock Updates
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Solution Overview
Problem
Conventional phase interpolators in integrated circuits face challenges in generating and updating the phase selection code at higher frequencies, leading to glitches and false frequency locks due to asynchronous code changes with respect to input clock phases, especially when operating at frequencies greater than 2 GHz.
Innovation Solution
A system that includes a sensing circuit to determine a delay code and a variable delay circuit to generate a delayed phase interpolator code, ensuring it has a known phase relationship with input clock phases, thereby preventing glitches by switching the code only during a safe zone.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the phase selection code is updated during operation to track frequency changes, then the frequency tracking capability is improved, but glitches and false frequency locks occur due to asynchronous code changes with respect to input clock phases
Solution Approach 1:
The patent introduces a delay element that delays the phase selection code by a predetermined time period, ensuring that the code is updated only during safe zones when all input clock phases are at the same logic level. This preliminary timing adjustment prevents asynchronous code changes that cause glitches, while still allowing frequency tracking to occur during valid update windows.
2Productivity
If the clock frequency is increased to operate at higher frequencies (greater than 2 GHz), then the productivity is improved, but the phase selection code cannot be updated in time due to reduced update window, leading to glitches
Solution Approach 1:
The delay element pre-adjusts the timing of phase selection code updates to occur during safe zones, ensuring reliable updates even at high frequencies where the update window is reduced.
Solution Approach 2:
The patent utilizes periodic safe zones that occur regularly in the clock cycle when all input phases are at the same logic level. By synchronizing code updates to these periodic safe zones, the system maintains reliable updates at high frequencies without requiring continuous update capability.
3Loss of time
If the phase selection code update window is reduced at higher frequencies, then the time consumption is reduced, but the code may not be updated during the safe zone, causing glitches
Solution Approach 1:
The delay element proactively adjusts the code update timing to align with safe zones before the update actually occurs, ensuring that even with reduced time windows, updates happen at the correct moment when all input phases are stable at the same logic level.
Data Source
AI summary
An integrated circuit device includes a sensing circuit configured to determine a delay code from a plurality of delay codes using a phase interpolation (PI) code and a plurality of input clock phases, a variable delay circuit coupled to the sensing circuit and configured to generate a variable delay based on the delay code and generate a delayed PI code using the PI code and the delay code, the delayed PI code corresponding to a code obtained from adding the variable delay to the PI code, and a phase interpolator coupled to the variable delay circuit and configured to generate an output clock phase from the plurality of input clock phases using the delayed PI code.