Phase Interpolator Clocking With Injection Locking for Skew Correction

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Solution Overview

Problem

Data communication systems face challenges in reducing skew and jitter in clock signals, which affect the synchronization and accuracy of data transfers in communication systems like passive optical networks (PONs).

Innovation Solution

The system employs a phase interpolation method using a combination of phase interpolators and an injection locked oscillator to generate multiple phase signals, correcting for both static and dynamic skew. This approach provides a higher number of phase signals with improved linearity and reduced skew, enhancing the accuracy of clock signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If phase interpolators are used to offset transmit phase over time and frequency, then the SERDES can transmit data at the same frequency as far-end peer device, but static and dynamic skew of interleaved clock paths affects sampling margins

Engineering Contradiction:
Improvephase adjustment capabilityVSAvoidsampling margins
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The system divides the clock signal generation into multiple independent phase interpolators, each handling a specific phase offset. By segmenting the clock paths and independently controlling each interpolator, the system achieves fine-grained phase adjustment while maintaining synchronization accuracy and reducing skew effects on sampling margins.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system employs feedback mechanisms to continuously monitor and adjust the phase offsets in real-time. By measuring the actual phase differences and dynamically correcting them, the system compensates for static and dynamic skew, ensuring optimal sampling margins are maintained despite variations in operating conditions.

Inventive Principle:
Principle #23Feedback

2Reliability

If multiple phase signals are generated to improve sampling margins, then skew and jitter reduction is achieved, but the system complexity increases

Engineering Contradiction:
Improvesampling marginsVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system combines multiple phase interpolators and clock paths into a unified synchronized output. By merging the phase-adjusted signals from multiple interpolators and using centralized control logic, the system achieves skew and jitter reduction while minimizing the increase in overall system complexity through integrated design.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The phase interpolators are designed to perform multiple functions: phase offset adjustment, skew compensation, and jitter reduction. By making these components multi-functional, the system achieves multiple performance improvements without proportionally increasing complexity, as the same hardware structures serve multiple purposes.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed solution effectively reduces skew and jitter in clock signals, improving the synchronization and accuracy of data transfers in communication systems. It achieves this by generating multiple phase signals with improved linearity and skew correction, thereby enhancing the overall performance of data communication systems.

Implementation Method 1

The system employs a phase interpolation method using a combination of phase interpolators and an injection locked oscillator to generate multiple phase signals

Methodology Applied
Scientific EffectPhase interpolation:

Implementation Method 2

The system employs a phase interpolation method using a combination of phase interpolators and an injection locked oscillator to generate multiple phase signals

Methodology Applied
Scientific EffectInjection locking:

Data Source

PatentUS12316336B2Systems for and methods of phase interpolation
Publication Date: 2025.05.27 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US12316336B2 patent drawing
  • US12316336B2 patent drawing
  • US12316336B2 patent drawing

AI summary

A system includes a first phase interpolator, a second phase interpolator, and a circuit. The circuit is configured to receive a first signal and a second signal provided by the first phase interpolator and a third signal and a fourth signal provided by the second phase interpolator. The first circuit is configured to provide at least eight phase signals, each of the eight phase signals being at a respective phase angle in response to the first signal, the second signal, the third signal and the fourth signal.