Phase-Inverted Delay Circuit for Low-Area Signal Synchronization
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Solution Overview
Problem
Existing delay circuits require a large area and high current on integrated circuits due to the need for a long delay chain to synchronize low frequencies and an additional delay circuit at high frequencies, leading to inefficiencies in chip design.
Innovation Solution
A delay circuit that generates two phase-shifted signals in inverted fashion, allowing for synchronization with an input signal using half the maximum delay time required, thereby reducing the length of the delay chain and current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a long delay chain is used to synchronize low frequencies, then synchronization accuracy is improved, but area and current consumption increase
Solution Approach 1:
The patent inverts the conventional approach by generating two phase-shifted signals in opposite directions (one advanced, one delayed) instead of using a single long delay chain. This allows the circuit to achieve the same synchronization range with half the delay elements, reducing area while maintaining accuracy.
Solution Approach 2:
The delay chain is segmented into two symmetric halves that operate in opposite directions. Instead of one long sequential delay chain, the circuit uses two shorter chains working simultaneously, one producing phase-advanced signals and the other phase-delayed signals, thereby reducing total area.
2Measurement precision
If a long delay chain is used to synchronize low frequencies, then synchronization accuracy is improved, but current consumption increases
Solution Approach 1:
By inverting the delay direction and using symmetric phase-advanced and phase-delayed signals, the circuit achieves full synchronization range with half the number of delay elements. Since current consumption in delay chains is proportional to the number of elements, this halves the current usage while maintaining precision.
Solution Approach 2:
Segmenting the delay chain into two symmetric halves reduces the total number of active delay elements from N to N/2. Each half operates independently with half the elements, and their combined output provides the full synchronization range, directly reducing current consumption.
3Adaptability or versatility
If an additional delay circuit is added for high frequencies, then synchronization capability is improved, but device complexity increases
Solution Approach 1:
The symmetric delay chain structure serves multiple functions simultaneously: it handles both low and high frequency synchronization, generates both phase-advanced and phase-delayed signals, and provides full synchronization range without requiring additional frequency-specific circuits. This multi-functionality eliminates the need for separate delay circuits for different frequency ranges.
Solution Approach 2:
By generating signals in both phase directions from a single delay chain, the circuit achieves universal frequency coverage. The phase-advanced path handles high frequencies while the phase-delayed path handles low frequencies, allowing one circuit to replace what would traditionally require multiple frequency-specific circuits.
Data Source
AI summary
A delay circuit includes a delay device, to which an input signal is supplied. A first phase-shifted signal can be generated by the delay device, which is delayed by a first delay time with respect to the input signal, and a second phase-shifted signal can be generated, which is delayed by a second delay time with respect to the input signal. The delay device is configured such that the first and second phase-shifted signal can be generated in inverted fashion with respect to one another at an output terminal of the delay device after a delay of the input signal by a delay time.