Phase-Locked Signal Thresholding for Jitter-Resistant Clock Synchronization
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Solution Overview
Problem
Existing semiconductor devices face issues with unnecessary generation of phase-locked signals due to jitter and noise, which affect the synchronization of operations within the device.
Innovation Solution
The solution involves setting a short first set period using a compensation code during the initial operation and a longer second set period using an offset code to generate and stop the phase-locked signal based on the phase difference between reference and feedback clocks, thereby preventing unnecessary signal generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If phase-locked signal generation is continuously enabled to ensure synchronization, then synchronization reliability is improved, but unnecessary signal generation due to jitter and noise increases
Solution Approach 1:
The patent applies preliminary action by establishing phase difference thresholds (first threshold during initial operation, second threshold during normal operation) before actual phase-locked signal generation occurs. The detection circuits continuously monitor phase differences and only trigger signal generation when differences exceed these pre-set thresholds, preventing unnecessary signal generation due to jitter and noise while maintaining synchronization reliability.
2Measurement precision
If phase detection is performed continuously with high precision to detect small phase differences, then measurement precision is improved, but operational complexity and interference increase
Solution Approach 1:
The patent applies local quality by implementing different detection precision levels for different operational phases. During initial operation, a first phase difference threshold is used with corresponding detection sensitivity, while during normal operation, a second phase difference threshold (different from the first) is applied. This localized adjustment of detection characteristics optimizes measurement precision for each operational stage without unnecessarily increasing overall system complexity.
Data Source
AI summary
An electronic device includes a phase detection circuit configured to detect a difference between the phases of a reference clock and a feedback clock and a phase-locked signal generation circuit configured to generate a phase-locked signal based on the results of the detection of the difference between the phases of the reference clock and the feedback clock. The phase-locked signal generation circuit is configured to generate the phase-locked signal when the difference between the phases of the reference clock and the feedback clock is equal to or smaller than a first phase difference after the start of an initial operation and configured to stop the generation of the phase-locked signal when the difference between the phases of the reference clock and the feedback clock is equal to or greater than a second phase difference, which is greater than the first phase difference, after outputting the phase-locked signal.