Phase/Frequency Locked Loop Switching for Low-Spur Clock Recovery
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Solution Overview
Problem
Existing phase/frequency locked loops face challenges in adapting to varying data rates and bandwidth requirements, leading to issues with spurious frequency content in recovered clock signals, which affects their usability across different communication standards like HD-SDI and SD-SDI.
Innovation Solution
A phase/frequency locked loop apparatus and method that includes a phase detector with an accumulator for phase error and a loop filter to adjust the phase of a signal, and a frequency locked loop with a counter module for frequency error, enabling flexible operation by switching between over-sampling and clock and data recovery mechanisms based on data rate, using reconfigurable logic or integrated circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If over-sampling is used to generate recovered clock signal, then lower bit rate operation is enabled, but excessive spurious frequency content is introduced
Solution Approach 1:
The patent combines phase detection and frequency detection capabilities into a single phase/frequency detector unit. This merged detector can operate in different modes (phase-locked loop or frequency-locked loop) depending on the data rate, allowing the system to handle both low and high bit rate operations while managing spurious content through appropriate detection mode selection
Solution Approach 2:
The detector is designed to dynamically switch between phase detection mode and frequency detection mode based on the operating conditions. At lower data rates, phase detection is used with over-sampling, while at higher data rates, frequency detection is employed, enabling the system to adapt its detection mechanism to minimize spurious frequency content across different operating scenarios
2Device complexity
If conventional clean-up PLL is used, then system complexity is reduced, but it cannot handle excessive spurious frequency content
Solution Approach 1:
The patent changes the detection parameters by switching between phase detection and frequency detection modes. This parameter change allows the system to handle excessive spurious frequency content that would otherwise preclude the use of conventional clean-up PLLs, while still maintaining relatively simple system architecture through the use of a single reconfigurable detector
3Object-generated harmful factors
If CDR circuit is used for high bit rate, then spurious frequency content is reduced, but more robust phase/frequency detector is required
Solution Approach 1:
The phase/frequency detector is designed as a universal unit that can perform both phase detection and frequency detection functions. This multi-functionality allows the system to achieve reduced spurious frequency content through frequency detection at high bit rates while avoiding the need for separate robust detectors, as the same detector unit adapts its operation based on the data rate
Data Source
AI summary
A phase/frequency detector module allows operation as either a phase locked loop or a frequency locked loop. As a phased locked loop (PLL), the phase detector module is configured to decode phase differences between a reference signal and a voltage controlled oscillator (VCO) signal into phase correction signals that are updated at the rate of the VCO signal. An accumulation of the phase correction signals is implemented to form an accumulated phase error signal, which is then sampled at a lower rate than the VCO signal to accommodate slower components of the PLL, such as a digital to analog converter (DAC). As a frequency locked loop (FLL), the phase detector module is configured with frequency counters, so that frequency error may instead be detected. Any reduction of gain caused by the frequency counters is inherently equalized by the phase detector module.