Low-skew channel bonding via phase-measuring FIFO buffer

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Solution Overview

Problem

Conventional high-speed serial interface (HSSI) bonding techniques face challenges in achieving low channel-to-channel skew, especially at higher data rates, as they often introduce additional jitter and are not effective for bonding across non-adjacent channels.

Innovation Solution

The use of phase-measuring first-in-first-out (FIFO) buffer circuits to generate phase-measurement signals, which are then used by a channel-bonding control circuit to generate bit-slip or clock-slip control signals, allowing for adjustments in bit delays and clock phases to achieve low-skew bonding across multiple channels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional HSSI bonding techniques are used, then channel bonding is achieved, but additional jitter is introduced and skew control becomes difficult at higher data rates

Engineering Contradiction:
Improveskew controlVSAvoidjitter introduction
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent replaces conventional mechanical/analog skew adjustment methods with a digital phase-measuring FIFO buffer system. The FIFO buffer measures phase differences between channels and applies digital bit-slip adjustments, eliminating the jitter introduced by conventional analog techniques while achieving precise skew control at high data rates

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent implements a feedback mechanism where phase-measuring FIFO buffers continuously monitor the phase relationships between bonded channels and dynamically adjust bit positions through bit-slip control. This closed-loop feedback system maintains low skew while avoiding the jitter problems of open-loop conventional methods

Inventive Principle:
Principle #23Feedback

2Adaptability or versatility

If conventional bonding techniques are used, then adjacent channels can be bonded, but bonding across non-adjacent channels is not effective

Engineering Contradiction:
Improvechannel bonding flexibilityVSAvoidskew control
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent creates a universal bonding system that can handle both adjacent and non-adjacent channels through the same phase-measuring FIFO mechanism. The system measures and compensates for phase differences regardless of channel position, enabling flexible bonding configurations while maintaining precise skew control through digital adjustment

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Speed

If higher data rates are used, then transmission speed increases, but skew control becomes more challenging and jitter increases

Engineering Contradiction:
Improvedata rateVSAvoidskew control
Core Design Contradiction:
SpeedVSManufacturing precision

Solution Approach 1:

The patent replaces rate-dependent analog skew control with a digital phase-measuring FIFO system that operates independently of data rate. The FIFO buffer and phase measurement mechanism maintain consistent performance across different data rates, enabling high-speed transmission while preserving precise skew control through digital bit-slip adjustment

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS10291442B2Low-skew channel bonding using phase-measuring FIFO buffer
Publication Date: 2019.05.14 ALTERA CORP
  • US10291442B2 patent drawing
  • US10291442B2 patent drawing
  • US10291442B2 patent drawing

AI summary

Circuits and methods are disclosed for low-skew bonding of a plurality of data channels into a multi-lane data channel. In one embodiment, phase-measuring first-in first-out buffer circuits buffer pre-buffer parallel data signals and generate phase-measurement signals. A channel-bonding control circuit receives the phase-measurement signals and generates bit-slip control signals. Transmission bit-slip circuits slip integer numbers of bits based on the bit-slip control signals. Bypass registers may be used when the integer number of bits is greater or equal to the parallel width of a lane. In another embodiment, the channel-bonding control circuit receives the phase-measurement signals from the phase-measuring FIFO buffer circuits and generates clock-slip control signals. Clock slip circuits controllably slip parallel clock signals by integer numbers of unit intervals of a serial clock signal. Various other aspects, features, and embodiments are also disclosed.