Phase-Mixer Delay Circuit for Uniform Clock Synchronization
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Solution Overview
Problem
Conventional delay circuits exhibit duty cycle step variations and non-uniform delay step sizes, which cause reliability and robustness issues as clock frequencies increase, particularly in synchronizing clock signals.
Innovation Solution
The proposed delay circuit includes a coarse delay circuit coupled with a fine delay circuit that uses signal drivers with differing drive strengths and a phase mixer to generate an output signal with reduced duty cycle error and improved fine delay step uniformity, adjusting the delay based on phase differences detected by a phase detector and controlled by a controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fine delay circuits are used to adjust delay timing, then delay adjustment capability is provided, but duty cycle step variations and non-uniform delay step sizes occur causing reliability issues
Solution Approach 1:
The delay circuit is divided into a coarse delay circuit with multiple delay stages and a fine delay circuit with selectable delay paths. The coarse delay circuit provides gross delay adjustment through series-connected delay stages, while the fine delay circuit provides precise delay tuning through selectable parallel paths. This segmentation allows independent optimization of each section to achieve both uniformity and reliability.
Solution Approach 2:
The fine delay circuit dynamically selects between multiple delay paths based on control signals, enabling continuous delay adjustment. The circuit transitions between different delay configurations by activating specific delay paths, providing smooth and uniform delay steps without the duty cycle variations present in conventional static delay circuits.
2Productivity
If clock frequency is increased to improve productivity, then processing speed increases, but duty cycle step variance and non-uniform delay steps cause reliability issues
Solution Approach 1:
A phase detector compares the phase of the input clock signal with the output clock signal and generates feedback control signals. This feedback mechanism continuously monitors synchronization status and adjusts the delay circuit parameters to maintain accurate timing even at high clock frequencies, eliminating the reliability issues caused by duty cycle variations.
Solution Approach 2:
The delay circuit dynamically changes its delay parameters by selecting different delay paths and adjusting the number of active delay stages based on the detected phase difference. This parameter adjustment capability allows the circuit to maintain uniform delay steps and accurate duty cycle across varying clock frequencies, ensuring reliable signal synchronization.
3Measurement precision
If coarse delay circuit with series delay stages is used, then coarse delay adjustment is achieved, but fine delay precision is insufficient
Solution Approach 1:
The delay circuit is divided into a coarse delay circuit with multiple delay stages and a fine delay circuit with selectable delay paths. The coarse delay circuit provides gross delay adjustment through series-connected delay stages, while the fine delay circuit provides precise delay tuning through selectable parallel paths. This segmentation allows independent optimization of each section to achieve both uniformity and reliability.
Solution Approach 2:
The fine delay circuit introduces an additional dimension of delay adjustment by providing multiple parallel delay paths with different delay characteristics. Instead of simply increasing the number of series stages, the circuit uses parallel path selection to achieve fine delay precision, reducing the overall circuit complexity while maintaining high precision.
Data Source
AI summary
Apparatuses, methods, and delay circuits for delaying signals are described. An example apparatus includes a fine delay circuit configured to provide an output signal based on a ratio of a first input signal and a second input signal. The fine delay circuit including a phase mixer circuit including first signal drivers configured to receive the first input signal. The fine delay circuit further including second signal drivers configured to receive the second input signal, where at least two of the first signal drivers have different drive strengths and at least two of the second signal drivers have different drive strengths.