Phase Mixing Delay Loop for Precise Clock Synchronization
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Solution Overview
Problem
In semiconductor apparatuses, asynchronous delays between internal clock signals and system clock signals lead to phase discrepancies, which existing delay locked loop circuits struggle to fully synchronize, affecting data communication efficiency.
Innovation Solution
A phase mixing circuit is introduced, comprising multiple inverters and selection circuits that adjust the coupling of clock signals based on weight bits and their inverted signals, enabling precise phase mixing to synchronize internal clock signals with system clock signals through a combination of coarse and fine delay locking operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing delay locked loop circuits are used to synchronize internal clock signals with system clock signals, then phase synchronization is achieved, but asynchronous delays cannot be fully compensated resulting in residual phase discrepancies
Solution Approach 1:
The delay locked loop circuit is segmented into multiple independent delay cells (first delay cell, second delay cell, third delay cell, fourth delay cell) that can be individually controlled. Each delay cell processes a portion of the clock signal path, allowing granular adjustment of delay amounts to precisely compensate for asynchronous delays and achieve complete phase synchronization.
Solution Approach 2:
The delay cells are configured with dynamic control capabilities through selection circuits that can selectively couple different delay paths based on operational requirements. The circuit transitions from static delay compensation to dynamic adjustment, enabling the system to adaptively compensate for varying asynchronous delays and achieve optimal phase synchronization under different operating conditions.
2Measurement precision
If multiple delay cells are added to improve phase synchronization precision, then asynchronous delay compensation is enhanced, but device complexity increases
Solution Approach 1:
Multiple delay cells are merged into a unified delay locked loop architecture where the first and second delay cells process one clock signal path while the third and fourth delay cells process another path. The selection circuits merge control functions to manage all delay cells, reducing overall system complexity while maintaining high precision phase synchronization capabilities.
Solution Approach 2:
The delay cells are designed with universal functionality to handle different clock signal paths and delay requirements. Each delay cell can operate independently or in combination with others, and the selection circuits provide multi-functional control capabilities, allowing the same structural elements to serve multiple purposes and reducing the need for additional specialized components.
Data Source
AI summary
A phase mixing circuit includes a first driver comprising 2n inverters configured to drive a first clock signal, where n is a positive integer, and a first selection circuit configured to couple each of the 2n inverters of the first driver to a first mixing node, on the basis of a weight having first to 2nth bits. The phase mixing circuit also includes a second driver comprising 2n inverters configured to drive a second clock signal and a second selection circuit configured to couple each of the 2n inverters of the second driver to the first mixing node, on the basis of an inverted signal of the weight.