Phase-Mode Superconducting Logic for Low-Power Clocked Circuits
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Solution Overview
Problem
CMOS technology-based digital circuits face limitations in device size reduction and high power consumption due to static power dissipation and current leakage, even when inactive, leading to inefficiencies in high-performance digital systems.
Innovation Solution
The use of Josephson junction-based phase-mode logic devices that operate with sinusoidal clock signals and return-to-zero clock signals, eliminating the need for bias resistors and allowing for zero static power dissipation, leveraging AC power and persistent phase-encoded data across clock cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If CMOS technology is used for digital circuits, then device integration is achieved, but power consumption increases due to static power dissipation and current leakage
Solution Approach 1:
The patent transitions from CMOS technology operating at room temperature to superconducting technology operating at cryogenic temperatures, fundamentally changing the operating parameters to eliminate resistive power loss. This temperature parameter change enables zero static power dissipation while maintaining high device integration through Josephson junction-based circuits.
Solution Approach 2:
The patent replaces the CMOS transistor-based logic system with a Josephson junction-based superconducting logic system. This substitution eliminates the need for bias resistors and enables AC-powered operation with zero static power consumption, directly addressing the power consumption issue while maintaining computational functionality.
2Speed
If CMOS circuits operate at high clock speeds, then processing performance improves, but power consumption increases due to dynamic and static power loss
Solution Approach 1:
The patent employs AC-powered Josephson junctions that operate through periodic sinusoidal clock signals with four distinct phases. This periodic action enables high-speed switching and signal propagation while consuming power only during active transitions, eliminating static power loss and reducing overall power consumption at high clock speeds.
Solution Approach 2:
The patent changes the operating temperature parameter to cryogenic levels, enabling superconducting operation with zero resistance. This parameter change allows high clock speed operation without the resistive power loss that plagues CMOS circuits, achieving both high speed and low power consumption simultaneously.
3Stability of the object's composition
If CMOS transistors maintain state even when inactive, then circuit functionality is preserved, but power is wasted due to state maintenance and current leakage
Solution Approach 1:
The patent extracts and removes the bias resistors from the circuit architecture, eliminating the source of static power consumption. The Josephson junction-based logic gates operate without requiring continuous bias current, allowing state maintenance without power waste and eliminating current leakage issues inherent in CMOS technology.
Solution Approach 2:
The superconducting circuits utilize persistent currents in superconducting loops to maintain state without external power input. The AC-powered Josephson junctions naturally oscillate and maintain their operational state through the inherent properties of superconductivity, eliminating the need for continuous power supply to maintain circuit state.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables low-power superconducting logic circuits with reduced power consumption and minimized glitches, maintaining state across multiple clock cycles, thus improving the efficiency and performance of digital systems.
Implementation Method 1
a plurality of Josephson junctions and at least one terminal for receiving a sinusoidal clock signal for providing power to the at least the plurality of Josephson junctions
Implementation Method 2
The device may further include at least one latch... The output of the at least one latch may be persistent across the at least four phases of the sinusoidal clock signal
Data Source
AI summary
A device including Josephson junctions, and a terminal for receiving a sinusoidal clock signal for providing power to the Josephson junctions, is provided. The device further includes a terminal for receiving an input signal, a clock terminal for receiving a return-to-zero clock signal, and at least one latch. The device also includes at least one logic gate including at least a subset of the Josephson junctions, for processing the input signal and the return-to-zero clock signal to generate a first signal for the at least one latch. Additionally, the device includes at least one phase-mode logic inverter for processing the return-to-zero clock signal to generate a second signal for the at least one latch. The device also includes an output terminal for providing an output of the at least one latch by processing the first signal and the second signal.