Phase-Offset CDR Circuit for Fast Lock and Lower Complexity
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Solution Overview
Problem
Existing clock and data recovery (CDR) circuits face challenges such as high complexity, bandwidth limitations, large area occupation, significant power consumption, and lengthy lock times due to the need for dedicated phase lock loops and feedback loops in recovering serial data and clock signals without an additional clock input.
Innovation Solution
A CDR circuit design that employs first and second sampling circuits, comparator circuits, and selection circuits to determine phase offset samples and generate an output word, utilizing a sampling clock and its inverse to capture phase-shifted samples and determine logic states for accurate data recovery without an additional clock input.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dedicated phase lock loop (PLL) circuit is used for clock and data recovery, then the circuit can reliably recover clock and data signals, but the device complexity and area occupation increase
Solution Approach 1:
The patent combines the clock recovery and data recovery functions into a single integrated circuit structure. The sampling circuits use the received serial data stream itself as the sampling clock, merging the clock generation and data sampling functions that were previously separate in traditional PLL-based CDR circuits. This integration reduces device complexity while maintaining recovery reliability.
Solution Approach 2:
The sampling circuits are designed to perform multiple functions: they simultaneously recover the clock signal and sample the data signal using the same circuit blocks. The first and second sampling circuits can operate in different modes (first edge-triggered and second edge-triggered) to achieve both clock recovery and data recovery without requiring dedicated separate circuits for each function.
2Reliability
If traditional feedback loop-based CDR circuits are used, then clock and data can be recovered, but the bandwidth is limited and lock time is lengthy
Solution Approach 1:
The circuit performs preliminary sampling of the serial data stream at multiple phase offsets before final data recovery. The first and second sampling circuits take phase offset samples in advance, allowing the system to quickly determine the correct sampling phase without waiting for traditional feedback loop convergence. This preliminary action enables faster lock time and higher bandwidth response.
Solution Approach 2:
The patent implements a simplified feedback mechanism where the phase offset samples are compared to determine logic state consistency. The selection circuit uses this comparison feedback to automatically select the correct sampling phase, providing rapid phase acquisition without the complex bandwidth limitations of traditional PLL feedback loops.
3Measurement precision
If oversampling is implemented in traditional CDR circuits, then sampling accuracy improves, but the circuit complexity and power consumption increase significantly
Solution Approach 1:
The sampling process is segmented into two distinct phases: first edge-triggered sampling and second edge-triggered sampling. Each sampling circuit is dedicated to one edge type, dividing the complex oversampling task into simpler, specialized sub-circuits. This segmentation maintains sampling accuracy while reducing overall circuit complexity compared to a single complex oversampling circuit.
4Reliability
If traditional CDR circuitry is used, then clock and data recovery is achieved, but the area occupation and power consumption are significant
Solution Approach 1:
The circuit merges clock recovery and data sampling into unified sampling circuits that perform both functions simultaneously. By using the received serial data stream as the sampling clock source, the circuit eliminates the need for separate clock generation and data sampling blocks, significantly reducing power consumption while maintaining full recovery capability.
Data Source
AI summary
A first sampling circuit takes phase offset first samples of a received serial data stream in response to a first edge of a sampling clock and a first comparator circuit determines whether the plurality of phase offset first samples have a same logic state. A second sampling circuit takes phase offset second samples of the received serial data stream in response to a second edge of the sampling clock, opposite the first edge, and a second comparator circuit determines whether the phase offset second samples have a same logic state. One of the first samples or one of the second samples is then selected in response to the determinations made by the first and second comparator circuits. A serial to parallel converter circuit generates an output word including the selected one of the first and second samples.