Phase-Based Priority Scheduler for Thread Group Execution
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Solution Overview
Problem
In multi-threaded computer architectures, existing scheduling methods lead to performance losses due to inconsistent waiting periods for memory load operations across threads, causing inefficiencies in processor utilization.
Innovation Solution
A method for scheduling priority among thread groups by determining their operational phases and adjusting priority descriptors to skew execution, allowing thread groups to operate in different phases and reduce waiting times for memory load operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a second thread is scheduled to execute during the waiting period of the first thread, then processor utilization is improved, but execution inconsistency and performance loss occur when execution cycles differ
Solution Approach 1:
The patent implements dynamic priority adjustment where thread priorities are not fixed but change based on execution phase and waiting period status. The scheduler dynamically modifies priority descriptors to skew execution phases, allowing the system to adapt to varying execution cycle lengths and prevent performance loss from execution inconsistency.
Solution Approach 2:
The patent changes the priority parameter of threads based on their execution phase and waiting period status. By adjusting priority descriptors dynamically, the system modifies execution scheduling parameters to ensure that threads with longer waiting periods maintain higher priority, thereby resolving execution inconsistency while maintaining high processor utilization.
2Device complexity
If threads execute in the same phase with same priority, then scheduling is simple, but all threads wait for memory load operations simultaneously causing performance loss
Solution Approach 1:
The patent introduces asymmetric priority assignment where threads in the same phase are assigned different priority levels based on their waiting period characteristics. This asymmetry causes threads to skew into different execution phases, preventing simultaneous waiting and improving processor performance while adding minimal scheduling complexity.
Solution Approach 2:
The patent implements periodic phase advancement where threads progress through execution phases in a structured manner. By controlling which threads advance to the next phase based on priority and waiting period status, the system creates a periodic execution pattern that prevents simultaneous blocking while maintaining manageable scheduling complexity.
3Speed
If high priority threads preempt low priority threads during memory load waiting, then critical threads execute faster, but low priority threads experience extended waiting periods
Solution Approach 1:
The patent applies preliminary phase skewing to high priority threads before they enter memory load waiting periods. By pre-adjusting the execution phase of critical threads, the system ensures they can preempt effectively when needed while the scheduler has already prepared priority descriptors to minimize the impact on low priority threads' waiting periods.
Data Source
AI summary
A streaming multiprocessor (SM) in a parallel processing subsystem schedules priority among a plurality of threads. The SM retrieves a priority descriptor associated with a thread group, and determines whether the thread group and a second thread group are both operating in the same phase. If so, then the method determines whether the priority descriptor of the thread group indicates a higher priority than the priority descriptor of the second thread group. If so, the SM skews the thread group relative to the second thread group such that the thread groups operate in different phases, otherwise the SM increases the priority of the thread group. f the thread groups are not operating in the same phase, then the SM increases the priority of the thread group. One advantage of the disclosed techniques is that thread groups execute with increased efficiency, resulting in improved processor performance.