Phase Recovery Filtering for Equalization-Induced Timing Corruption
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Solution Overview
Problem
Digital receiver equalization can corrupt phase detection during timing recovery, particularly due to excessive correction, which is not effectively mitigated by existing methods, leading to potential timing corruption and system complexity.
Innovation Solution
A system and method that acquire in-phase and quadrature samples of the received signal, with a transition detection unit generating signals indicative of logic state transitions and an equalization detect signal to selectively mitigate potential corruption by filtering out excessive equalization corrections, ensuring accurate phase recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If digital receiver equalization is employed to correct intersymbol interference, then signal quality is improved, but phase detection accuracy deteriorates due to timing corruption
Solution Approach 1:
The patent segments the equalization correction process into multiple discrete correction levels applied at different stages. By dividing the correction into segments (e.g., coarse correction followed by fine correction), the system can apply corrections without overwhelming the phase detector, thus maintaining phase detection accuracy while still improving signal quality.
Solution Approach 2:
The patent implements dynamic adjustment of equalization correction strength based on detected signal conditions. The correction amount is varied in real-time according to the received signal quality and phase detection results, allowing the system to optimize between signal quality improvement and phase detection accuracy under different operating conditions.
2Reliability
If complex front end hardware is designed to minimize equalization corrections, then timing corruption is reduced, but device complexity increases
Solution Approach 1:
The patent replaces complex analog front-end hardware with digital signal processing techniques. Instead of using complex physical equalization circuits in the analog domain, the system uses digital equalization algorithms that can be implemented in software or programmable logic, achieving similar timing recovery accuracy with reduced hardware complexity.
Solution Approach 2:
The patent implements a multi-functional digital processing unit that performs both equalization and phase detection functions. This universal block handles multiple tasks (equalization, timing recovery, phase measurement) that would traditionally require separate dedicated hardware circuits, thereby reducing overall device complexity while maintaining timing recovery accuracy.
3Reliability
If baud rate timing recovery is used to avoid timing information at symbol edges, then timing corruption is avoided, but productivity decreases due to inefficient use of timing information
Solution Approach 1:
The patent introduces an intermediary processing stage between the raw received signal and the phase detector. This intermediary block performs preliminary equalization and conditioning of the signal, creating an optimized intermediate representation that preserves timing information from symbol edges while removing equalization-induced distortions, thus enabling both stable timing recovery and efficient data extraction.
Data Source
AI summary
A system and method are provided for phase recovery of a signal received by a receiver having digital equalization. A sample acquisition unit periodically acquires a plurality of I and Q samples of the received signal. The sample acquisition unit includes a delay portion to enable selective mutual comparisons between a current I sample ID0, a first preceding I samples ID1, and a second preceding I sample ID2. A transition detection unit generates at least one transition detect signal responsive to the ID1, ID0, and Q samples. The transition detect signal indicates a logic state transition in the received signal between the ID1 and ID0 samples. A transition filtering unit generates an equalization detect signal indicative of excessive equalizing correction of the received signal at the ID0 sample, and selectively passes in response the transition detect signal as a timing output signal.