Phase-Rotated Clock Handoff for Low-Latency Async Data Transfer
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Solution Overview
Problem
Existing solutions for data handoff between asynchronous clock domains suffer from high latency and increased power consumption, which are detrimental in low-latency applications like switch fabrics in data centers.
Innovation Solution
A circuit system that uses a phase rotator and a controller to generate a gapped read clock and its inverted version, allowing the flip flop to selectively sample incoming data using these clocks, ensuring sufficient timing margin and avoiding metastability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional data handoff methods are used between asynchronous clock domains, then timing margin requirements are met, but latency increases
Solution Approach 1:
The patent applies dynamics by making the clock selection dynamic rather than static. The system selectively switches between the gapped read clock and the inverted gapped read clock based on real-time phase alignment conditions. This dynamic clock selection allows the system to adapt to varying timing conditions, achieving both sufficient timing margin and reduced latency by using the most appropriate clock edge for each data sampling operation.
Solution Approach 2:
The patent changes the parameter of clock phase selection by generating two complementary clocks (gapped read clock and inverted gapped read clock) with opposite phase relationships to the source clock. By monitoring phase alignment conditions and selecting between these two clock parameters, the system can optimize both timing margin and latency performance depending on the current operational state.
2Reliability
If conventional data handoff methods are used between asynchronous clock domains, then data stability is ensured, but power consumption increases
Solution Approach 1:
The system employs dynamic clock gating controlled by a phase alignment detector. By dynamically enabling or gating the gapped read clock and inverted gapped read clock based on actual phase alignment conditions, the system minimizes unnecessary clock switching and associated power consumption while maintaining data stability. The clock gating mechanism ensures clocks are only active when needed for valid data sampling.
Solution Approach 2:
The phase alignment detector automatically monitors the relationship between the source clock and read clock, and the clock selector autonomously chooses between the gapped and inverted clocks based on this monitoring. This self-service mechanism eliminates the need for external control logic, reducing overall system power consumption while maintaining reliable data handoff.
3Reliability
If Gray Coding is used for data handoff, then metastability is prevented, but latency and power consumption increase
Solution Approach 1:
The patent introduces a intermediary phase alignment detector and dynamic clock selector between the source clock domain and the read clock domain. This intermediary mechanism monitors phase relationships and dynamically adjusts clock selection to prevent metastability conditions without requiring the latency-intensive Gray Coding scheme. The intermediary acts as a smart gatekeeper that ensures reliable data transfer while minimizing delays.
4Reliability
If handshaking techniques are used for data handoff, then timing requirements are met, but multiple cycles of latency are introduced
Solution Approach 1:
The system performs preliminary action by pre-generating both the gapped read clock and the inverted gapped read clock in advance, and continuously monitoring their phase alignment with the source clock. This preliminary preparation eliminates the need for post-data-transfer handshaking delays, as the appropriate clock is already ready and selected before data sampling occurs, thereby meeting timing requirements without introducing multiple cycles of latency.
Data Source
AI summary
Aspects of the subject disclosure may include, for example, a device including a phase rotator configured to receive a read clock, a flip flop configured to obtain an incoming data stream, and a controller. The controller may be configured to control the phase rotator to perform phase rotation of the read clock based on information-carrying level transitions in the incoming data stream, cause a gapped read clock and an inversion of the gapped read clock to be derived in accordance with the phase rotation, where the gapped read clock being derived via gapping operations associated with the read clock, and output clock selection signals that enable the flip flop to selectively sample the incoming data stream using the gapped read clock and the inversion, thereby facilitating a data handoff between asynchronous clock domains. Other embodiments are disclosed.