Oversampled Phase Rotator Clock Synthesis for Low-Jitter USB 3.0
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Solution Overview
Problem
Conventional fractional N frequency synthesizers are complex and introduce unacceptable levels of jitter and frequency spurs in clock signals, failing to meet stringent timing requirements of communication standards like USB 3.0.
Innovation Solution
A circuit incorporating a programmable phase rotator and frequency divider that updates the phase difference between input and output signals at a frequency greater than the output signal, reducing jitter and enabling generation of non-integer multiple clock frequencies within a phase-locked loop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional fractional N frequency synthesizers are used to generate multiple clock frequencies, then frequency generation capability is achieved, but jitter and frequency spurs in the output clock signal increase to unacceptable levels
Solution Approach 1:
The patent applies dynamics by making the phase update frequency variable and adaptable. The phase rotator updates at a frequency that is a multiple of the input clock frequency (e.g., 2x, 4x, or higher), allowing the system to dynamically adjust the update rate based on the specific frequency generation requirements. This dynamic approach enables the system to maintain low jitter and frequency spurs while generating multiple clock frequencies, resolving the contradiction between frequency versatility and signal quality.
2Adaptability or versatility
If phase-locked loops are used to generate multiple frequencies, then frequency synthesis capability is achieved, but circuit complexity and size increase
Solution Approach 1:
The patent merges multiple frequency synthesis functions into a single phase rotator circuit. Instead of using separate phase-locked loops for each frequency generation, the invention combines the frequency division and phase rotation functions into one integrated circuit block. This single circuit can generate multiple clock frequencies by updating the phase difference between input and output signals at an elevated update frequency, thereby reducing overall circuit complexity and size while maintaining frequency synthesis capability.
Solution Approach 2:
The phase rotator circuit is designed with universal functionality to perform multiple frequency synthesis tasks. By updating the phase difference at a frequency that is a multiple of the input clock frequency, the same circuit can generate various output frequencies (e.g., both 480 MHz and 2.5 GHz for USB 3.0) without requiring separate dedicated circuits for each frequency, thus achieving multi-functionality with reduced complexity.
3Ease of operation
If conventional frequency synthesizers update phase at output frequency, then circuit operation is simplified, but jitter in the output clock signal increases
Solution Approach 1:
The patent applies parameter changes by modifying the phase update frequency parameter. Instead of updating the phase difference at the output clock frequency (which causes high jitter), the invention updates the phase at a frequency that is a multiple of the input clock frequency (e.g., 2x, 4x, or higher). This parameter change in the update frequency fundamentally reduces the jitter in the output clock signal while maintaining ease of circuit operation, as the same phase rotator architecture is used but with a different operational parameter.
Data Source
AI summary
Circuits and systems for generating multiple frequencies are disclosed. In some embodiments, a circuit can include a first node, a second node, and a programmable phase rotator. The first node can receive a first signal having frequency f1, and the second node can output a second signal having frequency f2 that is different from f1. In some embodiments, a frequency divider can generate a third signal having frequency f3 based on the second signal. In some embodiments, a frequency divider can generate the first signal based on a reference signal having frequency f4. The programmable phase rotator can be capable of updating, at an update frequency that is substantially equal to f1 and/or f4, a phase difference between the first signal and the second signal. In some embodiments, the circuit can be part of a USB (Universal Serial Bus) 3.0 physical layer (PHY) circuit.