Phase Rotator LUT Calibration for Low-Jitter Shared PLLs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional phase rotator systems in Phase-Locked Loops (PLLs) face challenges in linearization, particularly when trying to minimize jitter and power consumption, often requiring separate PLLs for transmitters and receivers, which increase power and area requirements, and struggle with continuous calibration and compensation for temperature, voltage, and aging effects.
Innovation Solution
A single PLL system with phase rotators connected outside the feedback loop, utilizing adaptable Look-Up Tables (LUTs) continuously updated by a control device to modify operating code based on phase response characteristics, allowing for iterative linearization and compensation for errors caused by temperature changes, voltage shifts, and aging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate PLLs are used for transmitter and receiver to reduce phase shift, then phase accuracy is improved, but power consumption and circuit area increase greatly
Solution Approach 1:
The patent merges the functions of separate transmitter and receiver PLLs into a single shared PLL circuit. The phase rotators are placed outside the feedback loop of this shared PLL, allowing both transmitter and receiver to utilize the same phase-locked loop infrastructure while maintaining independent phase rotation capabilities for frequency offset compensation.
Solution Approach 2:
The shared PLL circuit is designed to serve multiple functions - it provides phase locking for both transmitter and receiver operations. The phase rotators, positioned outside the feedback loop, enable the system to perform frequency offset compensation for both transmit and receive paths using the same PLL core, thereby reducing overall power consumption and circuit area.
2Reliability
If phase rotator is placed within feedback loop to filter non-linear responses, then jitter is reduced, but ability to generate multiple clock frequencies is restricted
Solution Approach 1:
The patent extracts the phase rotators from within the PLL feedback loop and positions them outside the loop. This extraction allows the feedback loop to maintain its jitter-filtering function while the phase rotators independently provide frequency offset compensation. The phase rotators operate on the PLL output signal without interfering with the feedback mechanism that suppresses jitter.
Solution Approach 2:
The system is segmented into distinct functional blocks: the PLL feedback loop handles phase locking and jitter suppression, while the phase rotators handle frequency offset compensation. This segmentation allows each component to perform its specialized function optimally without compromising the other capability.
3Ease of manufacture
If clock rate of digital core is used as update rate for phase rotator, then implementation is simplified, but update rate is restricted and jitter floor increases
Solution Approach 1:
The patent implements a dynamic update mechanism where the phase rotator update rate is decoupled from the digital core clock rate. The system can adaptively adjust the update rate of the phase rotator based on jitter characteristics and system requirements, allowing faster updates when needed to reduce jitter floor without being constrained by the fixed digital core clock frequency.
4Measurement precision
If foreground calibration is performed to linearize phase rotator, then initial accuracy is improved, but system cannot be recalibrated for aging and environmental changes
Solution Approach 1:
The patent implements continuous background calibration that operates throughout the system's operational lifetime. The calibration process is performed in the background without requiring system shutdown or interruption of normal operations. This continuous calibration adapts to aging effects, temperature variations, and voltage shifts, maintaining linearization accuracy over time.
Solution Approach 2:
The system employs feedback-based calibration where phase response characteristics are continuously monitored and used to adjust the Look-Up Table (LUT) settings. This feedback mechanism enables the system to detect drift due to aging or environmental changes and automatically compensate for them, maintaining optimal performance without manual intervention.
Data Source
AI summary
Circuits, controllers, and techniques are provided for reducing non-linearities in a phase rotator. A circuit, according to one implementation, includes a single Phase-Locked Loop (PLL) circuit having a main path and a return path forming a feedback loop. The circuit also includes one or more phase rotators connected to an output of the single PLL circuit outside the feedback loop and one or more adaptable Look-Up Tables (LUTs) populated with operating code to be provided to the one or more phase rotators for defining operating characteristics of the one or more phase rotators. Furthermore, the circuit includes a control device configured to receive phase response characteristics from the one or more phase rotators. The control device is further configured to modify the operating code of the one or more adaptable LUTs based on the phase response characteristics to reduce non-linearities of the one or more phase rotators.