Phase-Selectable Clock Synchronization for Shorter Lock Time
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Solution Overview
Problem
In modern integrated circuits, synchronizing a local clock signal with an external clock signal is inefficient due to the length of the delay line required, which can bottleneck systems, especially at high speeds and when multiple frequencies are needed.
Innovation Solution
Generating three internal clock signals from an external clock signal, separated by 1tCK or 2tCK, and selecting one based on timing characteristics for synchronization, reducing the total length of the delay line and improving locking efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single internal clock signal is used for synchronization, then the circuit structure is simple, but the lock time is excessively long and system efficiency is reduced
Solution Approach 1:
The patent divides the single internal clock signal into three separate internal clock signals (ICK0, ICK1, ICK2) that are phase-separated by 1tCK or 2tCK. This segmentation allows the system to select the most appropriate clock signal for synchronization based on timing characteristics, thereby reducing lock time without significantly increasing overall circuit complexity.
2Adaptability or versatility
If the delay line length is increased to accommodate multiple frequencies, then frequency adaptability is improved, but the lock time increases and system bottlenecks occur
Solution Approach 1:
The delay line is segmented into three parallel paths, each generating a clock signal with different phase separation (1tCK or 2tCK). This allows the system to adapt to multiple frequencies by selecting the appropriate phase-separated clock signal, while keeping each individual delay path relatively short, thus maintaining system efficiency and avoiding bottlenecks.
Solution Approach 2:
The system dynamically selects which of the three internal clock signals to use for synchronization based on timing characteristics and frequency requirements. This dynamic selection mechanism enables the system to adapt to varying frequency demands without being constrained by a fixed, overly long delay line, thereby maintaining high productivity.
3Adaptability or versatility
If multiple internal clock signals with different frequencies are generated, then device operation flexibility is improved, but the synchronization complexity and power consumption increase
Solution Approach 1:
Instead of generating multiple completely independent clock signals, the patent segments a single internal clock into three phase-separated signals (ICK0, ICK1, ICK2) that share the same frequency base but differ by 1tCK or 2tCK. This approach provides operational flexibility for different timing requirements while significantly reducing power consumption compared to generating multiple independent high-frequency clock sources.
Data Source
AI summary
There is provided a system for comparing the phase characteristics of three generated clock signals, each having a unique phase relationship with an original clock signal, with the original clock signal and to select a signal based on the proximity of the phase characteristic of the three signals to the original signal. The selection of a clock signal that most closely approximates the original significantly reduces lock time when attempting to synchronize an internal clock with an external clock. Additionally, there is provided a method for comparing three clock signals with an original clock signal and selecting from the three clock signals one that is approximately in phase with the original clock signal.