Phase-Selectable High-Speed Divider With Lower Clock Power
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Solution Overview
Problem
Existing programmable divider circuits face limitations in speed and flexibility due to feedback loops and synchronization requirements, which restrict the maximum possible speed and efficiency of signal division, especially when handling high-speed clock signals.
Innovation Solution
A phase selectable divider circuit that utilizes a multiplexer to select and generate clock signals with varying phases and pulse widths, allowing for dynamic configuration of pulse-width control circuits to achieve desired divide ratios and output frequencies with reduced timing loops and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional dual modulus prescalar or loadable backward counter is used for programmable division, then the divider can provide flexibility and programmability, but the feedback loop and synchronization circuitry limit the maximum operating speed
Solution Approach 1:
The divider is segmented into multiple independent parallel paths, each handling a specific divide ratio. Each path contains dedicated counters and logic that operate simultaneously without feedback loops, allowing the circuit to achieve high speeds while maintaining programmability through selective activation of paths.
Solution Approach 2:
All counter values and division ratios are pre-configured in the circuit before operation begins. The select circuit pre-determines which parallel path to activate based on the desired divide ratio, eliminating the need for runtime feedback and synchronization, thus maximizing operating speed.
2Adaptability or versatility
If multiple flip-flops are used to load the clock input for programmable division, then the divider can accommodate different divide ratios, but the clock input becomes heavily loaded and power consumption increases
Solution Approach 1:
The flip-flop resources are segmented into multiple groups, where each group serves a specific parallel division path. Only the flip-flops in the active path are clocked and consuming power at any given time, reducing overall power consumption while maintaining the ability to support multiple divide ratios through the select circuit.
Solution Approach 2:
The circuit uses periodic selection of active parallel paths based on the divide ratio requirement. The select circuit periodically activates only the necessary subset of flip-flops and logic elements, allowing inactive components to power down, thus reducing average power consumption while preserving full programmability.
3Adaptability or versatility
If feedback loop and synchronization circuitry are used to change modulus and reset counters, then the divider can be reconfigured for different ratios, but the timing loops are extended and glitches may occur
Solution Approach 1:
The reconfiguration capability is segmented across multiple independent parallel paths rather than achieved through a single feedback loop. Each path is self-contained with pre-configured counters, eliminating the need for feedback-based modulus changes and preventing glitches associated with synchronous resetting.
Solution Approach 2:
The feedback loop and synchronization circuitry are completely extracted from the design. Instead of using feedback to reconfigure the modulus, the invention uses a select circuit to choose from pre-configured parallel paths, removing the source of timing loops and potential glitches entirely.
Data Source
AI summary
A method for dividing a signal having a first frequency by a divide ratio includes selecting, based on the divide ratio, a first pulse width of at least one signal having a second frequency and being generated by at least a corresponding one of a plurality of pulse-width control circuits responsive to at least one signal having a second pulse width. The method includes selecting at least one of the plurality of pulse-width control circuits to be powered-on to generate the at least one signal. The at least one of the plurality of pulse-width control circuits includes a first pulse-width control circuit to generate a first signal having the first pulse-width, second frequency, and first phase. The first signal corresponds to a select circuit output signal having a first phase. The method includes selecting at least one other of the plurality of pulse-width control circuits to be powered-off.