Phase-Selective Deserializer Alignment for Inverted Clock Signals
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Solution Overview
Problem
High-speed semiconductor systems require efficient data transmission schemes to handle high bandwidth data communication, but existing pre-fetch schemes struggle with aligning data correctly when internal clock signals have different phases, leading to errors in data alignment.
Innovation Solution
A deserializer is designed with a data aligner, selection signal generator, and selection output unit to align data using internal clock signals with different phases, generating higher and lower aligned data, and selecting the appropriate alignment based on phase detection signals, ensuring accurate data alignment even when clock signals are inverted.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pre-fetch schemes are used to achieve high bandwidth data communication, then data transmission rate is improved, but data alignment accuracy deteriorates when internal clock signals have different phases
Solution Approach 1:
The system dynamically selects between different data alignment paths (higher aligned data or lower aligned data) based on the phase relationship between first and second internal clock signals. The selection signal generator detects the phase relationship and generates a selection signal that dynamically routes the appropriate aligned data to the output, allowing the system to adapt to varying clock phase conditions while maintaining high transmission rates and accurate data alignment.
2Productivity
If multi-phase clock signals are used to achieve parallel data output, then data transmission bandwidth is improved, but complexity of phase detection and selection increases
Solution Approach 1:
The selection signal generator implements a feedback mechanism by detecting the phase relationship between internal clock signals and generating a selection signal based on this detection. This feedback loop automatically adjusts the data alignment path selection according to the actual clock phase conditions, simplifying the overall control logic while maintaining high bandwidth operation through multi-phase clock signals.
Data Source
AI summary
Deserializers are provided. The deserializer includes a data aligner, a selection signal generator and a selection output unit. The data aligner is configured to align data in response to internal clock signals having different phases from each other to generate higher aligned data and lower aligned data. The selection signal generator is configured to detect a phase of one of the internal clock signals in response to a phase detection signal to generate a selection signal. The phase detection signal includes a pulse generated according to a write command signal and a write latency signal. The selection output unit is configured to output the higher aligned data or the lower aligned data as selected alignment data in response to the selection signal.