Phase-Selector Data Latch Circuit for Clock Sampling Accuracy
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Solution Overview
Problem
In interface systems and larger chips, maintaining synchronous clocks is challenging, leading to clock phase errors due to asynchronous clock signals, which result in timing violations and data sampling errors in flip-flops and data latch elements, especially when digital and analog circuits are combined.
Innovation Solution
A data latch circuit with a phase selector is introduced, comprising three flip-flops connected in series and a phase selector that generates a second clock signal based on the phase relation between the first and third clock signals, using a phase detector, filter, hysteresis buffer, and multiplexer to adjust the clock signal and prevent sampling errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If two successive data latch elements (flip-flops) are used to improve sampling accuracy, then data accuracy is improved, but sampling errors occur due to improper phase relation between clock signals
Solution Approach 1:
The patent introduces a phase selector that dynamically adjusts the phase of the second clock signal based on the phase relationship between the first and third clock signals. This dynamic phase adjustment ensures that the middle flip-flop samples data at the correct phase, preventing sampling errors while maintaining the three-stage latch structure for improved accuracy.
Solution Approach 2:
The phase selector implements a feedback mechanism by monitoring the phase relationship between clock signals and automatically adjusting the second clock signal's phase accordingly. This feedback control ensures that the clock phases remain properly synchronized, preventing timing violations and sampling errors in the multi-stage latch circuit.
2Reliability
If clock phase errors are solved through digital circuits by analyzing delays, then clock synchronization is improved, but device complexity increases
Solution Approach 1:
The phase selector acts as an intermediary component between the first and third clock signals, automatically adjusting the phase of the second clock signal. This intermediary device simplifies the overall system by providing a dedicated phase adjustment mechanism rather than requiring complex delay analysis and compensation throughout the entire digital circuit.
3Adaptability or versatility
If asynchronous clock signals are used in two clock generators, then design flexibility is improved, but timing violations occur in flip-flops
Solution Approach 1:
The phase selector dynamically adjusts the phase of the second clock signal based on the actual phase relationship between the first and third clock signals from different generators. This dynamic adaptation allows the system to handle asynchronous clock signals from multiple generators while ensuring proper timing compliance in the flip-flops, combining design flexibility with timing reliability.
Data Source
AI summary
The present invention provides a data latch circuit. The data latch circuit includes a first data latch unit, a second data latch unit, a third data latch unit, and a phase selector. The first data latch unit is used for latching a first input data according to a first clock signal and outputting a first output data. The second data latch unit is used for latching the first output data according to a second clock signal and outputting a second output data. The third data latch unit is used for latching the second output data according to a third clock signal and outputting an output data. The phase selector is coupled to the second data latch unit for generating the second clock signal to the second data latch unit according to phase relation between the first clock signal and the third clock signal.