Phase Shift Clock Signals for RFI Mitigation
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Solution Overview
Problem
High-speed electronic interfaces, such as those in memory devices, face challenges with asynchronous clock timing margin loss and duty cycle distortion due to channel losses and internal variations, leading to radio frequency interference (RFI) issues that increase with higher memory speeds, which conventional methods like frequency shifting or additional shielding fail to adequately address without performance drops or increased costs.
Innovation Solution
Implementing RFI mitigation circuitry that phase shifts clock signals based on configuration information, using resistors or data structures to determine delays for destructive interference between noise sources and mitigators, allowing surface layer routing and reducing RFI risk without the need for additional shielding or performance drops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory speed is increased to improve productivity, then data transfer rate is improved, but radio frequency interference increases
Solution Approach 1:
The patent applies phase shifting to clock signals to convert the harmful RFI effects into beneficial destructive interference patterns. By introducing controlled phase delays to specific clock signals based on their spatial relationship to antennas, the signals interfere destructively at antenna locations, reducing RFI while maintaining high-speed operation
Solution Approach 2:
The patent changes the phase parameter of clock signals dynamically. Configuration information determines specific phase shift amounts applied to different clock signals, allowing optimization of RFI mitigation while maintaining signal integrity and data transfer performance
2Object-generated harmful factors
If frequency shifting is used to mitigate RFI, then RFI is reduced, but performance drops
Solution Approach 1:
Instead of changing frequency, the patent changes only the phase parameter of clock signals. This phase shifting approach mitigates RFI through destructive interference while preserving the original signal frequency and timing characteristics, thus maintaining system performance
3Object-generated harmful factors
If additional shielding is implemented to reduce RFI, then RFI is reduced, but manufacturing cost increases
Solution Approach 1:
The patent replaces physical shielding mechanisms with an electronic/phased array approach. By using phase shifting circuitry to create destructive interference patterns, the need for additional PCB shielding layers or physical barriers is eliminated, reducing manufacturing complexity and cost
4Object-generated harmful factors
If PCB layers are increased to add shielding, then RFI is reduced, but device complexity increases
Solution Approach 1:
The patent substitutes electronic phase shifting for mechanical/physical layer additions. The RFI mitigation is achieved through signal processing in existing PCB layers rather than adding more physical layers, maintaining simple PCB architecture
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces RFI risk and maintains performance by applying phase shifts to clock signals, enabling surface layer routing and minimizing additional costs associated with increased PCB layers, while providing better performance than frequency shifting methods.
Implementation Method 1
phase shifts clock signals based on configuration information
Implementation Method 2
provide a delay between respective signals of the first and second sets based on RFI mitigation information associated with the respective signals
Data Source
AI summary
An example of an apparatus may include signal circuitry to provide a first set of one or more signals and a second set of one or more signals for an electronic device, and radio frequency interference (RFI) mitigation circuitry coupled to one or more of the signal circuitry, the first set, and the second set to provide a delay between respective signals of the first and second sets based on RFI mitigation information associated with the respective signals. Other examples are disclosed and claimed.