Phase-Shift PLL Circuit for Fine Clock Phase Alignment
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Solution Overview
Problem
Conventional phase locked loops (PLLs) face difficulties in finely adjusting clock signals, as they typically require increased power or rely heavily on process matching, making precise phase adjustments less than the time period of the output signal challenging.
Innovation Solution
The Phase-Shift-PLL incorporates a phase adjusting circuit with phase shifters and dividers to generate output signals that allow for fine phase adjustments of the output signal in increments less than the time period, independent of process matching, by dividing reference and feedback signals and applying phase shift control signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the VCO is run faster to achieve finer phase adjustment, then phase adjustment precision is improved, but power consumption increases and the system is limited by maximum operating speed
Solution Approach 1:
The invention segments the phase adjustment function into two independent parts: a coarse adjustment mechanism using the conventional VCO and a fine adjustment mechanism using separate delay lines. The delay lines are controlled by independent control signals, allowing fine phase adjustment without increasing VCO operating frequency, thus avoiding the power consumption penalty while achieving high precision phase control.
2Adaptability or versatility
If multiple VCO outputs at different phases are used, then phase adjustment range is improved, but the system becomes heavily dependent on process matching
Solution Approach 1:
The invention introduces delay lines as intermediary elements between the VCO output and the feedback path. These delay lines provide the phase adjustment function with much better process matching characteristics than direct VCO phase taps. The delay lines act as buffers that isolate the phase adjustment function from process variations, enabling wide phase adjustment range while maintaining reliability independent of process matching.
3Measurement precision
If delay blocks are added to the PLL, then fine phase adjustment is achieved, but the system becomes cumbersome and still suffers from poor process matching
Solution Approach 1:
The invention merges the delay line-based fine adjustment mechanism with the conventional VCO-based coarse adjustment mechanism into a unified phase control system. The phase detector output simultaneously controls both the VCO frequency and the delay line phases, creating an integrated system that achieves fine phase adjustment without the complexity of separate adjustment paths. This unified approach reduces device complexity while maintaining high precision.
Data Source
AI summary
A phase shift phase locked loop (PSPLL) are described. The phase shift PLL includes a PLL and a phase adjusting circuit coupled to the inputs of the PLL. The phase adjusting circuit has a first input, a first output, a second input, a third input, and a second output. The first output and the second output are coupled to a first input and a second input of the PLL, respectively. The second input of the phase adjusting circuit receives a feedback signal and the third input of the phase adjusting circuit receives a control signal. The phase adjusting circuit receives a reference signal and sends a first output signal and a second output signal based on the reference signal to the PLL to adjust a phase of an output signal of the PLL in an increment less than a time period of the output signal of the PLL.