FPGA SERDES Phase-Shift Sampling for CDR-Free USB 2.0
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Solution Overview
Problem
Conventional FPGAs face challenges in handling high-speed USB 2.0 mode due to limited capabilities in device connectivity and the need for CDR circuits, making it difficult to manage high-speed data transmission effectively.
Innovation Solution
A system with a host and a device featuring a field-programmable gate array (FPGA) with configurable logic blocks and a USB interface, including differential comparators to identify logic zero states, enabling high-speed data communication by oversampling data signals with clock speeds twice that of the data rate and phase shifting, facilitating transmission through a P-channel and N-channel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional FPGA uses GPIO to handle USB data transmission, then it can manage low-speed and full-speed modes, but it cannot effectively handle high-speed USB 2.0 mode at 480 Mbps
Solution Approach 1:
The patent segments the high-speed data transmission task into multiple parallel channels (P-channel and N-channel), each handling a portion of the data stream. This segmentation allows the FPGA to process 480 Mbps by dividing it into manageable streams that can be handled by existing GPIO capabilities, thus enabling high-speed support without requiring complete architectural redesign.
Solution Approach 2:
The patent introduces a new dimension of processing by implementing both serial and parallel processing paths. Data is received serially at high speed, then converted to parallel streams for processing through multiple channels, and finally reassembled. This dimensional transformation allows the system to achieve high-speed capability while using conventional FPGA resources.
2Speed
If an FPGA deploys a CDR (clock data recovery) circuit to handle high-speed USB 2.0 mode, then it can achieve 480 Mbps data transmission, but it consumes a large number of resources and reduces flexibility
Solution Approach 1:
The patent extracts the CDR functionality from the main data path and implements it as a separate, dedicated module. This extraction allows the clock data recovery function to be performed independently, reducing the resource burden on the main logic fabric and allowing other resources to be used for user-defined logic functions.
Solution Approach 2:
The patent designs the CDR circuit and associated logic to serve multiple functions: it handles clock recovery, data synchronization, and protocol identification. By making this module multi-functional, the patent reduces the need for separate dedicated circuits for each function, thereby reducing overall resource consumption while maintaining 480 Mbps capability.
3Speed
If a conventional FPGA uses standard serdes to handle high-speed data transmission, then it can achieve faster data rates, but it requires additional CDR circuits that complicate the system
Solution Approach 1:
The patent merges the serdes functionality with the existing USB protocol handling logic into a unified interface module. By combining these functions, the patent eliminates the need for separate CDR circuits that would otherwise be required, reducing system complexity while maintaining high-speed capability. The merged module handles both serial data reception and protocol-specific processing in a single integrated unit.
Data Source
AI summary
A method for providing a high-speed data communication between a host and field-programmable gate array (“FPGA”) is disclosed. The method, in one embodiment, is capable of identifying a data rate on a bus containing a P-channel and an N-channel operable to transmit signals in accordance with a high-speed Universal Serial Bus (“USB”) protocol. Upon sampling, by a first input deserializer, first two samples of data signals carried by the P-channel in accordance with a first clock signals clocking twice as fast as the data rate of the P-channel, a second input deserializer is used to sample the second two samples of data signals transmitted by the N-channel in accordance with a second clock signal running twice as fast as the data rate of the N-channel with a ninety (90) degree phase shift. The method subsequently forwards the data signals to one or more configurable logic blocks (“LBs”) in FPGA.