Phase-Shifted AD Clock Sampling for Radar Distance Precision
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Solution Overview
Problem
Conventional radar devices experience significant errors in distance calculation due to long sampling intervals, which affect the precision of peak center estimation and subsequently the measured distance to reflecting objects.
Innovation Solution
Increasing the sampling frequency of analog-to-digital (AD) conversion to reduce the sampling interval, allowing for more accurate peak center estimation by using multiple AD clocks with the same frequency but different phases for sampling, and storing data at different timings for subsequent processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the sampling frequency of AD conversion is increased, then the measurement precision of peak center time is improved, but the device complexity and circuit load increase
Solution Approach 1:
The patent divides the sampling process into multiple phases using different AD clocks with phase differences. Instead of using a single high-frequency clock, the system segments the sampling operation across multiple lower-frequency clocks that are phase-shifted, thereby achieving equivalent high sampling resolution without overloading a single circuit component.
Solution Approach 2:
The patent introduces dynamic phase shifting among multiple AD clocks to achieve effective high-frequency sampling. By dynamically coordinating the phase relationships between multiple clocks, the system achieves the timing resolution of a higher-frequency single clock while distributing the circuit load across multiple manageable components.
2Measurement precision
If the sampling interval is reduced by increasing sampling frequency, then the distance calculation error is reduced, but the data processing load and memory requirements increase
Solution Approach 1:
The patent segments the high-frequency sampling process into multiple lower-frequency sampling operations using phase-shifted clocks. This segmentation reduces the instantaneous data processing load on any single processing unit while collectively achieving the same effective sampling resolution, thereby managing memory and processing requirements more efficiently.
3Measurement precision
If multiple AD clocks with different phases are used for sampling, then the peak center estimation accuracy is improved, but the device complexity increases
Solution Approach 1:
The patent intentionally introduces asymmetric phase shifts among multiple AD clocks rather than using symmetric timing. This asymmetric phase distribution allows the system to achieve accurate peak center estimation by sampling at strategically different points in the waveform cycle, reducing the need for complex synchronization while maintaining measurement accuracy.
Data Source
AI summary
A first AD converter subjects an analog signal to AD conversion by a first AD clock, and a second AD converter subjects the same analog signal to AD conversion by a second AD clock that is shifted in phase from the first AD clock by half cycle. FF circuits store the AD conversion results of the first AD converter and the second AD converter by the first AD clock and the second AD clock, respectively. FF circuits store the data of the FF circuits by the first AD clock, separately. A DPRAM writes the respective data that are stored by the FF circuits by the first AD clock as a group of data, divides the group of written data into the respective data, and reads the respective data by a logic clock in twice to output the data to an integration circuit.