Duty Cycle Correction Circuit Using Phase-Shifted Clock Detection
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Solution Overview
Problem
Existing duty cycle correction circuits in semiconductor devices are large, complex, and consume high current, making them inefficient for precise clock duty cycle control, which is crucial for stable operations and image sensing applications.
Innovation Solution
A duty cycle correction circuit that includes a detection block to identify the duty cycles of two phase-shifted clocks and a correction block to generate corrected clocks with a 50:50 duty cycle ratio, using logic combination units and phase correction units to maintain the logic states of the corrected clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a duty cycle correction circuit is implemented to correct clock duty cycles, then the operation stability and performance are improved, but the circuit area increases, device complexity increases, and current consumption increases
Solution Approach 1:
The duty cycle correction circuit is divided into distinct functional blocks: a detection block that identifies duty cycle deviations and a correction block that generates corrected clocks. This segmentation allows each block to perform its specific function efficiently, reducing overall circuit complexity while maintaining correction effectiveness.
Solution Approach 2:
The patent introduces an intermediary detection block that monitors the duty cycle of input clocks and provides control signals to the correction block. This intermediary component enables precise control of the correction process without requiring complex direct control mechanisms, thereby reducing device complexity while improving operation stability.
2Reliability
If a duty cycle correction circuit is implemented to correct clock duty cycles, then the operation stability is improved, but the circuit area increases
Solution Approach 1:
By segmenting the correction circuit into detection and correction blocks with clearly defined functions, the patent minimizes the area required for each block. The detection block uses simple logic circuits to identify duty cycle issues, while the correction block applies targeted adjustments, together achieving stable operation with reduced total circuit area.
Solution Approach 2:
The correction block generates corrected clocks that are copies of the input clocks but with adjusted duty cycles. This copying approach allows the circuit to maintain the original signal characteristics while correcting only the duty cycle parameter, reducing the need for additional complex circuitry and thereby reducing overall circuit area.
3Reliability
If a duty cycle correction circuit is implemented to correct clock duty cycles, then the operation stability is improved, but the current consumption increases
Solution Approach 1:
The detection block operates periodically to monitor duty cycle deviations, triggering correction only when needed rather than continuously. This periodic operation reduces current consumption while maintaining operation stability, as the correction circuits are activated only during duty cycle anomalies rather than operating continuously.
Solution Approach 2:
The detection block automatically identifies duty cycle deviations and generates control signals for correction without requiring external intervention. This self-service mechanism eliminates the need for additional control circuits and continuous monitoring, thereby reducing current consumption while ensuring operation stability is maintained.
Data Source
AI summary
A duty cycle correction circuit includes a detection block suitable for detecting a duty cycle of a first clock in response to the first clock and a second clock, and a correction block suitable for generating a first corrected clock having a corrected duty cycle relative to the first clock and a second corrected clock having a corrected duty cycle relative to the second clock, based on a detection result of the detection block.