Phase-Shifted Clock Signals for SoC Power Stability
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Solution Overview
Problem
Artificial neural network (ANN) systems face challenges in maintaining power stability due to fluctuating supply voltage, particularly when the number of processing elements increases, leading to increased power consumption and potential system instability.
Innovation Solution
A system-on-chip (SoC) design that includes multiple neural processing units (NPUs) operating on different clock signals with phase-shifted phases to manage power consumption and stabilize supply voltage, utilizing a power management integrated circuit to dynamically adjust clock phases based on utilization rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of processing elements in the neural processing unit is increased to improve parallel processing performance, then the computational speed and processing capability are improved, but the instantaneous power consumption and supply voltage fluctuation increase
Solution Approach 1:
The patent applies periodic action by dividing the clock signal into multiple phase-shifted clock signals that are periodically distributed to different processing elements. This allows processing elements to operate in staggered phases rather than simultaneously, converting a single large power peak into multiple smaller, distributed power consumption patterns. The phase-shifted clock signals create a periodic operation schedule that smooths out instantaneous power demands while maintaining overall processing throughput.
2Productivity
If the number of processing elements is increased to handle more computational operations, then the computational capability is improved, but the stability of supply voltage deteriorates due to excessive peak power demand
Solution Approach 1:
The patent segments the single clock signal into multiple phase-shifted clock signals, and segments the operation of processing elements into different phases. This segmentation distributes the computational load and power consumption across multiple time phases, preventing any single moment from demanding excessive power that would cause voltage instability. Each processing element operates in a specific phase, dividing the overall power demand into manageable segments.
3Reliability
If the supply voltage is increased to ensure system stability during high power demand, then the system reliability is improved, but the power consumption of the neural processing unit rapidly increases
Solution Approach 1:
By implementing periodic phase-shifted operation, the system maintains stability during high computational loads without requiring continuously high supply voltage. The periodic distribution of operational phases ensures that peak power demands are temporally separated, allowing the supply voltage to remain stable at lower levels while still supporting high overall computational capability through accumulated processing across phases.
Data Source
AI summary
A system-on-chip (SoC) may comprise a semiconductor substrate; a first circuitry, disposed on the semiconductor substrate, provided for a first neural processing unit (NPU) configured to perform operations of an artificial neural network (ANN) model; a second circuitry, disposed on the semiconductor substrate, provided for a second NPU configured to perform operations of an ANN model; and a third circuitry, disposed on the semiconductor substrate, configured to generate a control signal to selectively output one or more clock signals, wherein each of the first NPU and the second NPU may include a plurality of processing elements (PEs), and the plurality of PEs may include an adder, a multiplier, and an accumulator, and wherein the one or more clock signals may include an original clock signal and one or more phase-delayed clock signals based on a phase of the original clock signal.