Phase-Shifted Clock Synchronization for DDR Data Transmission
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Solution Overview
Problem
Current data synchronization methods in semiconductor apparatuses, such as DRAMs, face limitations in achieving high data transmission rates, particularly in DDR-DRAMs, where transmitting multiple data packets per clock cycle is challenging due to synchronization inefficiencies.
Innovation Solution
A synchronization apparatus utilizing phase-shifted clock signals in both serial-to-parallel and parallel-to-serial conversion devices, with a Phase Locked Loop (PLL) producing clock signals shifted by 0°, 90°, 180°, and 270° relative to a reference clock, enables synchronization of multiple data packets within a single clock cycle, and includes FIFOs for clock domain conversion and pointer management to maintain synchronization across different clock domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple data packets are transmitted per clock cycle to increase data transmission rate, then data transmission speed is improved, but synchronization complexity and reliability deteriorate
Solution Approach 1:
The patent segments the clock signal into multiple phase-shifted versions (0°, 90°, 180°, 270°) to independently synchronize multiple data packets. Each phase-shifted clock signal is dedicated to synchronizing specific data packets, allowing parallel transmission without interference and maintaining synchronization reliability while increasing data transmission rate.
Solution Approach 2:
The patent introduces dynamic phase-shifting of clock signals to adapt to different data packet synchronization requirements. The phase-locked loop continuously adjusts the phase of clock signals to maintain optimal synchronization timing, enabling reliable synchronization of multiple packets per clock cycle with varying timing requirements.
2Measurement precision
If separate training operations are used for write and read paths, then synchronization precision is improved, but device complexity and operation time increase
Solution Approach 1:
The patent implements a universal training operation that simultaneously configures both write and read path synchronization parameters. The same training sequence and adjustment mechanism are applied to both paths, allowing precise synchronization control while reducing operational complexity and eliminating the need for separate training procedures for each path.
Solution Approach 2:
The patent merges the training operations for write and read paths into a single unified process. By combining the configuration and adjustment steps for both paths, the system achieves synchronized operation without requiring duplicate training sequences, thereby reducing device complexity and operation time while maintaining synchronization precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances data transmission rates by allowing synchronization of multiple data packets per clock cycle, improving system performance and reducing the need for separate training operations in write and read paths, thereby increasing efficiency and reliability.
Implementation Method 1
Clock signals that are phase-shifted relative to one another are used for synchronizing data packets
Implementation Method 2
a Phase Locked Loop (PLL) producing clock signals shifted by 0°, 90°, 180°, and 270° relative to a reference clock
Data Source
AI summary
A synchronization apparatus for data synchronization and method for data synchronization is disclosed. One embodiment provides clock signals which are phase-shifted relative to one another are used for synchronizing data packets in a serial-to-parallel conversion device in a write path and equally for synchronizing data packets in a parallel-to-serial conversion device in a read path.