Phase-Shifted Clock Sampling Circuit for Low-Power Synchronization
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Solution Overview
Problem
Existing clock signal generation methods for data transmission between senders and receivers with independent internal clocks result in synchronization errors and high power consumption, especially in devices with limited power resources like smart cards and RFID devices.
Innovation Solution
An electric circuit that generates a plurality of clock signals with the same cycle duration but phase-shifted relative to each other, allowing for correlation with a digital signal to select an optimal clock-sampling signal, thereby reducing power consumption and achieving high synchronization accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high frequency clock signal is generated for sampling, then the data transmission synchronization is improved, but the power consumption increases
Solution Approach 1:
The clock signal generation is segmented into multiple phase-shifted clock signals (e.g., 4 clock signals with 90-degree phase shifts). Instead of using a single high-frequency clock, the system divides the clock generation into multiple lower-frequency phase-shifted signals, reducing power consumption while maintaining synchronization accuracy through selective use of appropriate clock phases.
Solution Approach 2:
The system changes the parameter of clock frequency by generating multiple clock signals with the same cycle duration but different phase shifts. By correlating a characteristic signal section of the digital signal with these phase-shifted clock signals, the system selects the optimal clock signal for sampling, achieving high synchronization accuracy without requiring a single high-frequency clock, thus reducing power consumption.
2Device complexity
If a single clock signal is used for sampling, then the device complexity is reduced, but the synchronization accuracy deteriorates
Solution Approach 1:
The system dynamically selects the appropriate clock signal from multiple phase-shifted clocks based on the correlation result with the digital signal's characteristic section. This dynamic selection allows the system to adapt to different signal conditions and achieve optimal synchronization accuracy without requiring a fixed complex clock generation system.
Solution Approach 2:
The correlation device provides feedback by comparing the digital signal's characteristic section with multiple phase-shifted clock signals. Based on this feedback, the system determines which clock signal provides the best synchronization, enabling accurate sampling while maintaining relatively simple device architecture.
Data Source
AI summary
An electric circuit (30) for generating a clock-sampling signal (CLK) for a sampling device (31) comprises a clock generator (1, 40, 50, 60) for generating a plurality of clock signals (21-24, 51-54, 61-64), a correlation device (L) for correlating a characteristic signal section (LE) of a digital signal (DS) with the plurality of clock signals (21, 22, 23, 24, 51-56, 61-64), and a selecting device (MX) for selecting one of the clock signals (21, 22, 23, 24, 51-55, 61-64) as the clock-sampling signal (CLK) for the sampling device (31) on the basis of the correlation by the correlation device (L). The clock signals (21-24, 51-54, 61-64) have the same cycle duration (T) and are phase-shifted with respect to each other. The sampling device (31) subsequently samples the digital signal (DS) with the clock-sampling signal (CLK).