Phase-Shifted Data Generation Circuit for High-Speed Equalized Transmission
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Solution Overview
Problem
As transmission frequencies increase, existing data generation circuits face challenges in maintaining signal amplitude and waveform integrity due to the size and power consumption issues associated with higher-order multiplexor circuits, such as the 4-to-1 MUX circuit, which necessitates additional circuits for generating cursors for feedforward equalization.
Innovation Solution
A data generation circuit comprising a storing circuit, a first selection circuit, and a second selection circuit that outputs data items in different phases in response to shifted clock signals, allowing the 4-to-1 MUX circuit to quadruple the modulation rate and generate both the main cursor and post cursor without the need for additional precursor and postcursor generation circuits, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a 4-to-1 MUX circuit is used to quadruple the modulation rate, then the transmission frequency is increased, but the data generation circuit increases in size and power consumption
Solution Approach 1:
The patent segments the data generation function across multiple clock domains. Instead of using a single complex 4-to-1 MUX circuit operating at quadrupled frequency, the invention divides the functionality into multiple simpler circuits operating at the original frequency but with phase-shifted clocks. This segmentation reduces the complexity of individual circuits while achieving the same overall data rate through parallel operation.
Solution Approach 2:
The patent introduces dynamic phase-shifting of clock signals to dynamically select which data path is active at any given time. By dynamically controlling the phase relationships between multiple clock signals, the system can achieve quadrupled data rates without requiring a static complex multiplexor structure, thereby reducing circuit complexity while maintaining high transmission frequency.
2Speed
If a 4-to-1 MUX circuit is used to quadruple the modulation rate, then the transmission frequency is increased, but power consumption increases
Solution Approach 1:
The patent segments the high-speed data generation task into multiple lower-speed parallel operations. By dividing the quadrupled data rate requirement into four separate data streams operating at the original frequency with phase shifts, each circuit segment consumes less power than a single circuit operating at quadrupled frequency, resulting in lower overall power consumption.
Solution Approach 2:
The patent employs periodic phase-shifting of clock signals to activate different data paths in a periodic manner. This periodic action allows the system to achieve high average data rates while each individual circuit element operates at lower frequency with periodic activation, reducing peak and average power consumption compared to continuous high-frequency operation.
3Reliability
If additional circuits are added for generating cursors for feedforward equalization, then signal integrity is maintained, but device complexity increases
Solution Approach 1:
The patent makes the phase-shifted clock distribution network serve multiple functions: it simultaneously enables high-speed data transmission and provides the timing signals needed for cursor generation in feedforward equalization. By making the clock distribution system universal, the patent eliminates the need for separate dedicated cursor generation circuits, maintaining signal integrity while avoiding additional complexity.
Solution Approach 2:
The patent merges the data generation function and the cursor generation function into a unified circuit architecture. By combining these functions that were previously implemented separately, the system achieves the necessary signal integrity for high-speed transmission without the overhead of additional dedicated circuits, thereby reducing overall device complexity.
Data Source
AI summary
According to one embodiment, a data generation circuit includes a storing circuit, and first and second selection circuits. The storing circuit is configured to store different data items and output the data items in different phases in response to clock signals. The first selection circuit is configured to select first data items one by one from the data items output from the storing circuit and output a first series of selected data items. The second selection circuit is configured to select second data items one by one, whose phase are different from the selected first data items, from the data items output from the storing circuit and output a second series of selected data items.