Phase-Shifted Deskew Circuit for Low-Power Data-Clock Alignment
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Solution Overview
Problem
Existing deskew systems face challenges in reducing chip size and power consumption while maintaining effective skew compensation, particularly with the phase picking method, which increases chip size and power consumption due to the need for multiple clocks and increased sampling frequencies.
Innovation Solution
A deskew system comprising a first and second voltage control delay, along with a skew compensation control unit, generates delayed data and clock signals in units of 90/N, where N is a natural number, to reduce the number of clocks required for sampling, thereby minimizing chip size and power consumption while enhancing skew compensation resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the phase picking method is used to reduce synchronization time and data operation speed loss, then skew compensation range is at least half of a cycle, but chip size and power consumption are increased due to multiple clocks and high sampling frequencies
Solution Approach 1:
The patent segments the clock signal into multiple phase-shifted clocks (CLK0, CLK1, CLK2, CLK3) with 90-degree phase differences. This segmentation allows the system to achieve wide skew compensation range using fewer sampling points, thereby reducing chip size while maintaining effective deskew performance
Solution Approach 2:
The patent employs periodic sampling using phase-shifted clocks where each clock samples at specific phases. This periodic action with optimized phase distribution enables the system to achieve complete skew compensation within a reduced number of sampling points, reducing both chip size and power consumption
2Measurement precision
If the number of clocks for sampling is increased to improve deskew performance, then skew compensation accuracy is improved, but chip size and power consumption are increased
Solution Approach 1:
The patent divides the sampling process into segments using 4 phase-shifted clocks instead of using a single high-frequency clock. This segmentation achieves the same skew compensation accuracy with reduced sampling frequency requirements, thereby reducing power consumption while maintaining measurement precision
Solution Approach 2:
The patent changes the sampling approach by introducing phase shift as a new parameter. Instead of increasing sampling frequency to improve accuracy, the system uses phase-shifted sampling which achieves the same accuracy with lower frequency requirements, thus reducing power consumption
3Measurement precision
If sampling frequency is increased to improve deskew performance, then skew compensation accuracy is improved, but power consumption is increased
Solution Approach 1:
The patent uses periodic sampling with phase-shifted clocks where each clock operates at a lower frequency but samples at different phases. This periodic action with phase diversity achieves the same effective sampling rate and accuracy as high-frequency single-clock sampling, but with reduced power consumption due to lower operating frequencies
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed system reduces chip size and power consumption while improving skew compensation resolution, maintaining phase differences between data and clock signals, and maintaining duty ratios, thus enhancing data transmission efficiency.
Implementation Method 1
a first voltage control delay unit (110), a second voltage control delay unit (120)... The first voltage control delay receives a data signal, generates N-numbered delayed data signals obtained by delaying a phase of the data signal
Data Source
AI summary
A deskew system includes a first voltage control delay receiving a data signal and generating N-numbered delayed data signals obtained by delaying a phase of the data signal in units of 90/N, where N is a natural number that is not less than 1. In response to a phase control signal, a second voltage control delay receives a clock and generates N-numbered delayed clocks by delaying a phase of the clock in units of 90/N. A skew compensation control unit generates a plurality of skew control signals to compensate for skew between the data signal and the clock based on the data signal, the N-numbered delayed data signals, the clock, and the N-numbered delayed clocks.