Phase-Shifted Interface Circuits for Low-Power Memory I/O
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The high power consumption ratio during signal transmission in semiconductor memory devices with three-dimensional stacking structures necessitates a method to reduce power consumption during data signal input and output.
Innovation Solution
A transmitter circuit comprising a clock generating circuit, pulse generating circuit, and overlapped multiplexing circuit, which generates multiple clocks and pulses to serialize bit values of input signals, and a receiver circuit with comparators and latches to decode bit values, reducing power consumption by using phase-shifted clocks and voltage equalization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If three-dimensional stacking structure with TSV is used to increase integration, then memory integration is improved, but power consumption ratio during signal transmission increases
Solution Approach 1:
The patent applies periodic action by using phase-shifted clocks to control the sequential transmission of data bits. Instead of continuous transmission, data is transmitted in periodic bursts synchronized with the phase-shifted clock signals, reducing overall power consumption while maintaining high integration benefits of the 3D stacking structure
Solution Approach 2:
The patent segments the data transmission process into multiple phases corresponding to different clock phases. Each phase handles specific data bits, allowing power to be activated only during necessary transmission windows rather than continuously, thus reducing the power consumption ratio while preserving integration advantages
2Use of energy by moving object
If multiple clocks with different phases are used to serialize bit values, then power consumption is reduced, but circuit complexity increases
Solution Approach 1:
The phase-shifted clock network serves multiple functions simultaneously: it controls the timing of data serialization, enables power gating for different data phases, and provides synchronization signals for the receiver. This multi-functionality reduces the need for separate control circuits, thereby limiting the increase in circuit complexity while achieving power reduction
3Use of energy by moving object
If overlapped multiplexing circuit is used to sequentially output overlapped signals, then power consumption is reduced, but signal transmission time increases
Solution Approach 1:
The patent changes the timing parameters of signal transmission by using phase-shifted clocks with optimized phase differences. This allows overlapped signals to be transmitted in a time-multiplexed manner where each signal occupies a specific time slot, reducing power consumption while maintaining acceptable transmission time through parameter optimization
Data Source
AI summary
A transmitter circuit of an interface circuit includes a clock generating circuit, a pulse generating circuit, an overlapped multiplexing circuit, and an output circuit. The clock generating circuit generates a plurality of clocks having different phases. The pulse generating circuit generates a plurality of pulses based on the plurality of clocks. The overlapped multiplexing circuit receives a plurality of input signals in parallel, and sequentially outputs a plurality of overlapped signals based on the plurality of clocks, the plurality of input signals, and the plurality of pulses, and each overlapped signal includes bit values of two input signals among the plurality of input signals. The output circuit serially outputs bit values of the plurality of input signals in series based on the plurality of overlapped signal.