Phase-Shifted PLL Circuit for Fractional Division Spur Suppression

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Solution Overview

Problem

Conventional phase-locked loops (PLLs) face challenges in fractional frequency division, leading to quantization errors and modulus errors, which affect spur suppression and frequency resolution, requiring trade-offs between bandwidth and spur suppression.

Innovation Solution

The proposed PLL incorporates phase shifters to generate shifted signals, phase frequency detectors to compare phases, charge pumps to control node voltage, a voltage-controlled oscillator, a frequency divider, and a circulator to selectively transmit signals, along with a modulator to push quantization errors to higher frequencies, thereby reducing modulus errors and suppressing in-band spurs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If an integer frequency divider is employed to perform fractional frequency division, then the PLL structure remains simple, but quantization errors occur and spur suppression deteriorates

Engineering Contradiction:

ImprovePLL structureVSAvoidfrequency division precision

Core Design Contradiction:

Device complexityVSManufacturing precision

Solution Approach 1:

The PFD operation is segmented into multiple non-overlapping enabling periods within one input signal cycle. Each PFD processes a specific time segment, allowing multiple phase comparisons without overlap. This segmentation enables fractional frequency division to be achieved through time-multiplexed operation of multiple PFDs, improving frequency precision while maintaining structural simplicity

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Multiple PFDs are enabled periodically with non-overlapping enabling periods. The first PFD is enabled during a first time period, the second PFD during a second time period, and so on, within one cycle of the input signal. This periodic time-multiplexed operation allows fractional frequency division to be performed with high precision without requiring complex hardware

Inventive Principle:

Principle #19Periodic action

2Measurement precision

If multiple phase frequency detectors with overlapping enabling periods are used, then frequency resolution improves, but modulus errors occur and in-band spurs increase

Engineering Contradiction:

Improvefrequency resolutionVSAvoidmodulus errors and in-band spurs

Core Design Contradiction:

Measurement precisionVSObject-generated harmful factors

Solution Approach 1:

Multiple PFDs are enabled periodically with non-overlapping enabling periods within one input signal cycle. The first PFD operates during a first time period, the second PFD during a second time period, ensuring that phase comparisons are performed sequentially without overlap. This periodic time-multiplexed operation achieves high frequency resolution while preventing modulus errors and in-band spurs that would result from overlapping operations

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

A circulator is introduced as an intermediary component to selectively connect the frequency divider output to different PFDs at different time periods. The circulator ensures that the output signal is transmitted to the appropriate PFD during its designated enabling period, preventing simultaneous access by multiple PFDs and thereby eliminating modulus errors and in-band spurs

Inventive Principle:

Principle #24Intermediary (Mediator)

3Object-generated harmful factors

If a modulator is added to push quantization errors to high frequency, then spur suppression improves, but device complexity increases

Engineering Contradiction:

Improvespur suppressionVSAvoidPLL structure

Core Design Contradiction:

Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

Multiple PFDs are enabled periodically with non-overlapping enabling periods within one input signal cycle. The first PFD is enabled during a first time period, the second PFD during a second time period, ensuring that phase comparisons are performed sequentially without overlap. This periodic time-multiplexed operation achieves high frequency resolution while preventing modulus errors and in-band spurs that would result from overlapping operations

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS7636018B2Phase locked loop with phase shifted input

Publication Date: 2009.12.22 UNITED MICROELECTRONICS CORP

AI summary

In a phase locked loop (PLL), phase shifters shift a phase of an input signal. Based on the phases of the input signal, the shifted signals, and a frequency division output signal, phase frequency detectors (PFDs) generate phase difference signals. In response to the phase difference signals, charge pumps (CPs) control output voltages thereof. Based on the output voltages of the CPs, a voltage controlled oscillator (VCO) outputs an output signal. A frequency divider divides the frequency of the output signal from the VCO to generate the frequency division output signal. A circulator outputs the frequency division output signal to one of the PFDs at a proper timing. A modulator reduces quantization errors of the frequency divider.