Phase-Shifted PWM Pulse Circuit for Fine Edge Timing Control
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Solution Overview
Problem
Existing pulse width modulated (PWM) signal control systems lack high-resolution control over the timing of rising and falling edges, particularly in applications requiring precise duty cycle control, leading to inefficiencies in output voltage regulation.
Innovation Solution
A circuit is developed that generates a set of phase-shifted clocks from a base set of higher frequency clocks, allowing for the generation of output PWM pulses with adjustable width by phase-aligning the edges using a CPU-controlled selection circuit and flip-flops, enabling precise control over the timing of PWM pulses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional PWM control systems are used, then the system is simple to implement, but the timing resolution of PWM pulse edges is insufficient
Solution Approach 1:
The clock signal is divided into multiple phase-shifted clock signals (e.g., 4 phases), and each phase is used to control different portions of the PWM pulse generation. This segmentation allows for finer timing resolution by selecting specific phase combinations, thereby improving edge timing precision without requiring a proportional increase in overall system complexity.
Solution Approach 2:
The system dynamically selects and combines different phase-shifted clock signals based on the desired PWM duty cycle and timing requirements. This dynamic selection mechanism enables high-resolution timing control by adaptively choosing the appropriate clock phases, achieving precision beyond what a single clock signal could provide while maintaining manageable circuit complexity through reusable logic blocks.
2Manufacturing precision
If high-resolution PWM edge control is implemented, then the precision of duty cycle control is improved, but the circuit complexity increases
Solution Approach 1:
The duty cycle control is segmented into multiple selectable time intervals using phase-shifted clocks. Each phase represents a discrete time segment, and by combining different phases, the system can precisely control the duty cycle in fine increments. This segmentation approach achieves high precision duty cycle control while keeping the circuit complexity manageable through systematic reuse of clock generation and selection logic.
Solution Approach 2:
The phase-shifted clock generation circuit and selection logic serve multiple functions: they provide timing references for PWM generation, enable duty cycle control, and support high-resolution edge timing. This multi-functionality reduces overall circuit complexity by having a single circuit structure perform multiple control tasks, thereby achieving precise duty cycle control without proportionally increasing complexity.
3Measurement precision
If phase-shifted clocks are generated from higher frequency clocks, then the timing resolution is improved, but the frequency synthesis complexity increases
Solution Approach 1:
The system uses periodic phase-shifted clock signals with fixed phase relationships (e.g., 90 degrees apart) to achieve high-resolution timing. By generating these clocks through systematic phase division and shifting of a master clock, the system achieves precise timing resolution without requiring complex frequency synthesis. The periodic nature of the clocks simplifies the synthesis process compared to arbitrary frequency generation.
Solution Approach 2:
The phase-shifted clocks are pre-generated and stored in a clock selection circuit before being used for PWM modulation. This preliminary generation of multiple phase references allows the system to simply select the appropriate phases for the desired timing resolution, rather than dynamically synthesizing frequencies during operation. This approach reduces frequency synthesis complexity by performing the phase generation work in advance.
Data Source
AI summary
A circuit includes a base pulse generator to generate a first pulse width modulated (PWM) pulse, a first clock generation circuit to generate M clocks of a first frequency and phase-shifted with respect to each other, and a second clock generation circuit to receive the M clocks and to generate N clocks each at a second lower frequency and the M clocks are phase-shifted with respect to each other. Each of a plurality of flip-flops includes a clock input to receive a different one of the N clocks, a data input coupled to receive the first PWM pulse, and a flip-flop output. A selection circuit includes a plurality of inputs and a selection circuit output. Each of the plurality of inputs is coupled to a corresponding flip-flop output. The selection circuit provides, responsive to a control signal, a selected one of the flip-flop outputs as the selection circuit output.