Phase-Shifted PWM Circuit for High-Resolution Printer Timing
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Solution Overview
Problem
Current printer technologies face challenges in achieving higher resolution across a wide range of printer base frequencies, as they require costly high-frequency integrated circuits and struggle to maintain pixel modulation performance, especially when transitioning from one base frequency to another.
Innovation Solution
The system employs multiple pulse width modulation (PWM) circuits that receive data input and phase-shifted clock signals to generate an output pulse width modulated signal, allowing for increased printer resolution by producing a set of clock signals with different phases and combining their outputs to produce a synchronized PWM signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a single high-frequency PWM circuit is used to increase printer resolution, then higher resolution is achieved, but the cost of the integrated circuit becomes prohibitive
Solution Approach 1:
The patent divides a single high-frequency PWM circuit into multiple lower-frequency PWM circuits operating in parallel. Each PWM circuit operates at the base frequency and generates pulse widths corresponding to different grey-scale levels. By segmenting the resolution requirement across multiple circuits rather than using one high-frequency circuit, the system achieves high resolution without requiring expensive high-frequency ICs.
Solution Approach 2:
The patent combines the outputs of multiple PWM circuits through logical OR operations to generate the final high-resolution PWM signal. The multiple PWM circuits are merged in terms of their functional output, where their collective pulse width modulation capabilities produce the equivalent effect of a single high-frequency circuit but at lower individual frequencies, reducing overall system cost.
2Manufacturing precision
If fixed delays are used to generate finely controlled pulse widths, then pulse width control is achieved, but pixel modulation performance varies across different printer base frequencies
Solution Approach 1:
The patent replaces static fixed delays with dynamic phase-shifted clock signals. Instead of using fixed IC gate delays that are invariant to frequency changes, the system uses clock signals with adjustable phases that can adapt to different base frequencies. The phase shifts are dynamically configured to maintain proper timing relationships across varying operating frequencies, enabling consistent performance.
Solution Approach 2:
The patent changes the timing parameters by using phase-shifted clock signals instead of fixed delay values. The phase shifts allow the system to adjust timing relationships dynamically, and the grey-scale level determination logic adapts to different base frequencies by interpreting the phase-shifted signals appropriately, maintaining consistent pixel modulation performance across frequency variations.
3Loss of time
If IC gate delays are used for delay implementation, then delay functionality is achieved, but significant variability occurs between different ICs due to process variations
Solution Approach 1:
The patent introduces phase-shifted clock signals as intermediaries to replace direct IC gate delay implementations. Instead of relying on the inherent and variable delay characteristics of IC gates, the system uses externally controlled clock signals with defined phase relationships as mediators to establish precise timing. This intermediary approach decouples the timing function from the variable IC gate delays, improving reliability.
Solution Approach 2:
The system incorporates feedback mechanisms where the phase-shifted clock signals and grey-scale level determination logic work together to compensate for timing variations. The feedback ensures that despite variations in individual component delays, the overall pulse width modulation achieves consistent results by adjusting the interpretation and combination of phase-shifted signals.
Data Source
AI summary
Systems in accordance with the presently claimed invention use input data to create an output pulse that is a fraction of the width of an input pulse. In some embodiments, the invention accepts input data and an input signal that has pulses of a specific frequency. In some embodiments, the invention uses a phase lock loop to create multiple signals of a higher frequency than the frequency of the input signal. Each of these multiple signals is offset by a certain phase from the other signals. In some embodiments, the invention synchronizes the input data to each of these multiple signals. The invention uses the phase difference between the multiple signals to create an output pulse as a function of the input data that is a fraction of the width of the input pulse.