Phase-Shifted PWM Generation for Asynchronous Synchronization
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Solution Overview
Problem
Conventional methods for generating multiple phase-shifted PWM signals struggle to maintain proper phase relationships between PWM signals following synchronization, as they rely on analog circuitry and simple motor control protocols, which are inadequate for advanced power conversion applications.
Innovation Solution
A system with separate phase offset counters in each PWM generator, independent of the duty cycle process, uses a master time base to reset phase counters and restart duty cycle counters, ensuring phase and duty cycle relationships are preserved during synchronization, generating repetitive single cycle PWM signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional analog circuitry or simple motor control protocols are used to generate phase-shifted PWM signals, then device complexity is reduced, but the ability to maintain proper phase relationships following synchronization is lost
Solution Approach 1:
The patent divides the PWM generation system into separate functional modules: a master time base generator that produces synchronization signals, individual PWM generators for each channel, and separate phase offset counters independent of duty cycle counters. This segmentation allows each module to be optimized independently while maintaining overall synchronization, resolving the contradiction between reliability and complexity.
Solution Approach 2:
The patent introduces a master time base as an intermediary that generates PWM cycle start signals to synchronize all PWM generators. This intermediary coordinate system allows multiple independent PWM channels to maintain proper phase relationships without requiring complex interconnections between them, achieving reliable synchronization with minimal complexity.
2Reliability
If phase shifting is integrated with duty cycle generation using time base counter preload or adders, then device complexity is reduced, but the ability to preserve duty cycle and phase relationships during asynchronous synchronization is compromised
Solution Approach 1:
The patent separates the phase offset counter from the duty cycle counter, creating independent counting mechanisms. The phase offset counter handles phase positioning while the duty cycle counter manages pulse width, allowing each to be optimized for its specific function without interfering with the other during synchronization events.
Solution Approach 2:
The patent pre-calculates and stores phase offset values in dedicated phase offset registers before synchronization events occur. When the master time base generates a PWM cycle start signal, these pre-prepared values are immediately loaded into phase offset counters, enabling rapid synchronization without complex real-time calculations during the synchronization event itself.
3Adaptability or versatility
If multiple PWM channels operate at different frequencies and phase shifts, then adaptability is improved, but maintaining phase relationships following synchronization becomes more difficult
Solution Approach 1:
The patent designs a universal master time base generator that can synchronize multiple PWM channels operating at different frequencies and phase shifts. The master time base produces a standardized PWM cycle start signal that all channels can use as a reference, allowing each channel to maintain its unique frequency and phase characteristics while still achieving coherent synchronization when needed.
Solution Approach 2:
The patent pre-configures phase offset registers with specific phase shift values for each channel before operation. This preliminary setup allows the system to quickly switch between different operating modes and maintain correct phase relationships during synchronization events without requiring complex real-time adjustment mechanisms.
Data Source
AI summary
Multiple pulse width modulation (PWM) generators each have a separate phase offset counter creating a phase shift. The phase shifting process is separated from the duty cycle generation process, thereby easing the task of preserving the duty cycle and phase relationships among the various PWM channels following an asynchronous external synchronization event. A master time base generates a PWM cycle start signal that resets the phase offset counters in each of the PWM generator circuits. The phase offset counter continues counting until it matches the respective phase offset value. Then, the associated duty cycle counter is reset and restarted. The duty cycle continues until its count matches the specified value at which time the duty cycle counter stops until reset by the terminal count from the phase offset counter. The output of the duty cycle comparators provide the output PWM signals as a repetitive series of single cycle PWM signals.