Random Number Generator With Phase-Shifted Ring Oscillators
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Solution Overview
Problem
Existing random number generators based on ring oscillators and metastability circuits suffer from low speed due to rare metastable events and slow phase movement, leading to insufficient entropy and randomness.
Innovation Solution
A random number generator design that includes multiple bistables connected to different phases of ring oscillators through delay lines, utilizing phase detectors and metastability circuits to stimulate bistables with less correlated signals, enhancing randomness through phase shifts and metastability detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional metastability circuits with ring oscillators are used, then truly random numbers can be generated, but the generation speed is low due to rare metastable events
Solution Approach 1:
The patent divides the single metastability circuit into multiple parallel metastability circuits (first, second, third, and fourth metastability circuits). Each circuit independently generates random bits through metastable events. By segmenting the system into multiple parallel paths, the overall random number generation speed increases while maintaining the quality of randomness from metastable events.
Solution Approach 2:
The patent introduces phase shifters that pre-adjust the phase of clock signals before they reach the ring oscillators and metastability circuits. This preliminary phase adjustment ensures that metastable events occur more frequently and at predictable intervals, improving the generation speed without sacrificing randomness quality. The phase shifters prepare the signals in advance to optimize the timing for metastable event occurrence.
2Reliability
If phase detectors are used to detect phase differences, then randomness can be improved, but the system complexity increases
Solution Approach 1:
The patent introduces phase shifters as intermediary components between the clock sources and the metastability circuits. These phase shifters mediate the phase relationships without requiring complex phase detection and correction mechanisms. By using simple phase-shifting elements rather than complex phase detectors, the system achieves the needed phase diversity for high entropy while keeping the overall circuit complexity manageable.
3Device complexity
If multiple ring oscillators operate at the same phase, then the circuit is simple, but the randomness is insufficient due to correlated outputs
Solution Approach 1:
The patent deliberately introduces asymmetric phase shifts between parallel metastability circuits using phase shifters. Instead of maintaining symmetric, identical phase relationships, the system uses asymmetric phase offsets to ensure that each metastability circuit experiences different phase conditions. This asymmetry breaks the correlation between outputs and enhances randomness quality while adding only minimal circuit elements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves randomness and speed by ensuring bistables are stimulated with different phase shifts, providing more independent and random processes, thus enhancing the entropy and reliability of generated numbers.
Implementation Method 1
at least one of the bistables is a metastability circuit, wherein at least one metastability circuit comprises a metastable generator of time intervals
Data Source
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AI summary
Random number generator (GL) comprises three ring oscillators (GP1, GP2, GP3) and seven bistables (UB1, UB2, UB3, UB4, UB5, UB6, UB7). The ring oscillators (GP1, GP2, GP3) comprise delay lines (LO1, LO2, LO3) closed in loops. The delay lines (LO1, LO2, LO3) comprise delays (EO) connected in series between inputs (i-LO1, i-L02, i-L03) and outputs (o-LO1, o-LO2, o-LO3) of the delay lines. Outputs (o-UB1, o-UB2, o-UB3, o-UB4, o-UB5, o-UB6, o-UB7) of the bistables (UB1, UB2, UB3, UB4, UB5, UB6, UB7) are connected to outputs (o1-GL, o2-GL, o3-GL, o4-GL, o-5GL, o6-GL, o7-GL) of the random number generator (GL). Inputs (i1-UB1, 12-UB1, 11-UB2, 12-UB2, 11-UB3, 12-UB3, 11-UB4, i2-UB4, 11-UB5, 12-UB5, 11-UB6, 12-UB6, 11-UB7, 12-UB7) of the bistables (UB1, UB2, UB3, UB4, UB5, UB6, UB7) are connected to the delay lines (LO1, LO2, LO3) of the ring oscillators (GP1, GP2, GP3) to outputs of selected delays (EO).