Phase-Shifted Sampling Equalization for Lower-Cost High-Rate ADCs
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Solution Overview
Problem
High-cost large-bandwidth analog-to-digital converters (ADCs) are required for phase-shifted sampling circuits to digitize signals with large bandwidth, necessitating a cost-effective solution while maintaining signal quality.
Innovation Solution
A phase-shifted sampling circuit with a primary sampler circuit, ADC circuit, and equalization circuit that reduces the bandwidth of the input signal, allowing for the use of cheaper ADCs and compensating for transfer function mismatches using a primary sampler equalizer sub-circuit configured as a linear periodic time-variant filter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large-bandwidth ADCs are used to digitize signals with large bandwidth in phase-shifted sampling circuits, then signal quality is maintained, but production costs increase
Solution Approach 1:
The patent divides the bandwidth requirement into two parts: the primary sampler circuit handles bandwidth reduction by filtering the input signal before ADC conversion, while the equalization circuit handles signal quality compensation by correcting transfer function mismatches. This segmentation allows the use of lower-bandwidth, cheaper ADCs while maintaining overall signal quality.
Solution Approach 2:
The patent introduces an equalization circuit as an intermediary component between the ADCs and the final output. This equalization circuit compensates for the transfer function mismatches introduced by the phase-shifted sampling paths, thereby maintaining signal quality without requiring expensive large-bandwidth ADCs.
2Productivity
If multiple ADCs sample at different phases to achieve higher sampling rates, then sampling rate increases, but device complexity increases
Solution Approach 1:
The patent merges the multiple phase-shifted sampling paths into a unified structure where the primary sampler circuit processes all input signals through a common bandwidth reduction stage. The equalization circuit then combines the outputs from multiple ADCs, compensating for phase-related mismatches. This merging approach achieves high sampling rates while controlling circuit complexity through shared components.
3Productivity
If phase-shifted sampling is used to achieve sampling rates exceeding single ADC capabilities, then sampling rate increases, but transfer function mismatches cause signal disturbances
Solution Approach 1:
The equalization circuit functions as a feedback mechanism that continuously compensates for transfer function mismatches between the phase-shifted sampling paths. By analyzing the output signals from multiple ADCs and applying corrective filtering, the system maintains signal quality while operating at enhanced sampling rates that would otherwise introduce distortions.
Data Source
AI summary
A phase-shifted sampling circuit is described. The phase-shifted sampling circuit includes a primary sampler circuit, an ADC circuit, and an equalization circuit. The primary sampler circuit includes an analog signal input, a first signal path, and a second signal path. The equalization circuit includes a primary sampler equalizer sub-circuit. The primary sampler equalizer sub-circuit is configured to compensate a mismatch between a transfer function associated with the first signal path and a transfer function associated with the second signal path. Further, a method of determining filter coefficients of an equalization circuit of a phase-shifted sampling circuit is described.